Low-power consumption power-on reset circuit

Abstract

The invention discloses a low power consumption power-on reset circuit, comprising two branches which are connected in parallel; a first branch comprises a first PMOS transistor, a first depletion type MOS transistor and a second depletion type MOS transistor; the source electrode of the first PMOS transistor is connected to a power supply; a grid is in short circuit connection with a drain electrode; the drain electrode of the first depletion type MOS transistor is connected to the drain electrode of the first PMOS transistor, and the node between the MOS transistor and the PMOS transistor is used as a first node; a first capacitor is connected between the first node and the ground; a second branch comprises a second PMOS transistor and a first NMOS transistor which are in parallel connection with a common grid; the source electrode of the second PMOS transistor is connected to the power supply; the drain electrode is connected to the drain electrode of the first NMOS transistor; the node between the second PMOS transistor and the first NMOS transistor is used as a second node for outputting a first reset signal; the lower-power consumption power-on reset circuit also comprises a third PMOS transistor; the third PMOS transistor is used for locking voltage of the first node according to a first reset signal. The low-power consumption power-on reset circuit adopts an electrical level triggering mode to generate a reset signal, has advantages of low power consumption and a strong anti-interference capability and compensates insufficiency in the current technology.

Description

technical field [0001] The invention relates to a low power consumption power-on reset circuit. Background technique [0002] When the chip is powered on, a reset signal needs to be generated to reset the internal registers. Commonly used power-on reset circuits include capacitor-resistor structures and level-triggered structures. The capacitor-resistance structure uses the time constant of the capacitor-resistance product as a delay to generate a reset signal. The advantage is that it does not consume power after the power-on process is over. The disadvantage is that it cannot generate a reset signal during the slow power-on process; the level-triggered structure combines the power supply voltage with Compared with the set voltage, when the power supply voltage is higher than the set voltage, the power-on reset signal is released. The advantage is that the reset signal has nothing to do with the power-on speed, and the disadvantage is that it needs to consume static power c...

AI Technical Summary

Problems solved by technology

The capacitor-resistance structure uses the time constant of the capacitor-resistance product as a delay to generate a reset signal. The advantage is that it does not consume power after the power-on process is over. The disadvantage is that it cannot generate a reset signal during the slow power-on process; the level-triggered structure combines the power supply voltage with Compared with the set voltage, when the power supply voltage is higher than the set voltage, the power-on reset signal is released. The advantage is that the reset signal has nothing to do with the power-on speed, and the disadvantage is that it needs to consume static power

Therefore, there is a lack of a low-power power-on reset circuit, which can not only have the advantages of a level-triggered structure, but also have lower power consumption.

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