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Vertical junction finfet device and method for manufacture

A device, n-type technology, applied in the field of junction field effect transistor devices, which can solve the problems of incompatibility of JFET devices and difficulty in controlling short-channel effects.

Active Publication Date: 2016-10-26
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such JFET devices suffer from the significant disadvantage of difficulty in controlling short-channel effects
Furthermore, the typical fabrication of JFET devices is incompatible with mainstream CMOS fabrication techniques

Method used

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  • Vertical junction finfet device and method for manufacture
  • Vertical junction finfet device and method for manufacture
  • Vertical junction finfet device and method for manufacture

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0009] now refer to Figures 1 to 15C , which shows the process steps for forming a vertical junction fin FET device. It will be understood that the drawings do not necessarily show features drawn to scale.

[0010] figure 1 A conventional bulk semiconductor substrate 10 is shown comprising a region 12 reserved to form a first polarity (n-channel) device (NFET) and a region 12 reserved to form an opposite second polarity (p channel) device (PFET) region 14. For example, silicon dioxide (SiO2) having a thickness of, for example, about 3 nm is deposited on substrate 10 using a chemical vapor deposition (CVD) 2 ) layer 16. Using photolithographic techniques well known to those skilled in the art, region 14 is blocked using an implant mask and an n-type dopant such as, for example, arsenic or phosphorous is implanted in region 12 to define n-type region 18 . This injection can for example provide a 1 x 10 18 at / cm 3 up to 5×10 18 at / cm 3 region 18 of the doping concentrat...

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PUM

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Abstract

The application relates to a vertical junction finfet device and method for manufacture. A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Description

technical field [0001] The present invention relates to integrated circuits and in particular to junction field effect transistor (JFET) devices fabricated using fins with vertical junctions. Background technique [0002] The prior art teaches the formation of integrated circuits using one or more junction field effect transistor (JFET) devices. The JFET device includes a junction formed below a gate conductor. The field is applied by the junction acting as the gate, rather than using an insulated gate as in conventional MOSFET type devices. Current flows between the gate region and the drain region in the doped semiconductor region located below the gate. By applying a voltage to the gate conductor, a charge-depleted region is formed in the doped semiconductor region to pinch off the conductive path and restrict the flow of current. Due to the lack of available mobile charges, the depletion region behaves as an insulating structure. [0003] Conventional JFET devices ar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/092H01L29/06H01L29/10H01L21/8238
CPCH01L21/823821H01L27/0924H01L29/0684H01L29/1033H01L29/66909H01L29/0657H01L29/165H01L27/098H01L29/8083H01L29/1066H01L29/1058H01L29/7832H01L29/66893H01L29/41741H01L21/283H01L29/41791
Inventor 柳青J·H·张
Owner STMICROELECTRONICS SRL