A mbist clock optimization method and device

Abstract

The present invention discloses a mbist clock optimization method and device wherein the method comprises the following steps: firstly, a clock providing unit provides a clock; and after that, a running mode configuration unit configures a logic circuit running mode, wherein the running mode comprises a function mode and a test mode; when the running mode configured by the running mode configuration unit is in the function mode, the logic circuit control unit sends the clock provided by the clock providing unit to a functional logic circuit and turns off the test logic circuit; when the running mode configured by the running mode configuration unit is in the test mode, the logic circuit control unit sends the clock provided by the clock providing unit to the test logic circuit and turns off the functional logic circuit. As the functional logic circuit and test logic circuit are completely separate, when a logic circuit is in working condition, the other logic circuits can be completely closed, thereby greatly reducing the consumption of chips in mbist tests and enhancing the stability of the tests.

Description

technical field [0001] The invention relates to the field of SOC chip design, in particular to an mbist clock optimization method and device. Background technique [0002] MBIST is the memory (memory) built-in self-test, which is the main test method for the internal memory of the chip. It embeds the test vector generation circuit and the comparison circuit into the chip, and only through a few simple peripheral control signals to start the internal memory. The test circuit automatically realizes the memory test, and automatically outputs the test comparison result after the test is completed. [0003] At present, the working clock of the memory test circuit is directly sharing the clock of the functional logic module. The advantage of this is that the clock of the functional circuit can be directly multiplexed without adding an additional clock structure, but this also leads to the memory test. The clocks of other non-mbist test circuits (that is, functional module logic b...

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Problems solved by technology

[0005] For this reason, it is necessary to provide a technical solution for mbist clock optimization to solve the problems of large power consumption, insufficient test power supply, and unstable test when performing mbist test due to the multiplexing of the working clock of the functional logic circuit in the existing chip. And other issues

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