Fault-tolerant type SDRAM control method for quickly responding to AHB access

Abstract

The invention provides a fault-tolerant type SDRAM control method for quickly responding to AHB access. An AHB bus interface is responsible for latching bus information and sending latched write data, if full-word write operation exists currently, the write data is sent to a multiplexer MUX1, if non-full word write operation exists currently, the write data is sent to a read-modification-write unit RMW, MUX1 judges whether full-word write exists currently, if yes, the write data 1 is directly transmitted into a shifting register link, and otherwise, the write data 2 processed by the RMW is transmitted into the shifting register link; MUX1 outputs the write data 3 into a data part of a write request shifting register link WR-SRC and into an encoder to generate write data 4, and the write data 4 is transmitted into a verification meta-part of the write request shifting register link WR-SRC; the data part of the write request shifting register link WR-SRC temporarily stores AHB bus write access requests to respond to an AHB bus in advance for quick release. The method integrates high performance and high reliability.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a fault-tolerant SDRAM control method for a SoC control chip to quickly respond to AHB access. Background technique [0002] With the continuous advancement of microelectronics technology to the ultra-deep sub-micron field, the design and manufacturing capabilities of high-speed, low power consumption, and high-density memory chips have been greatly developed. Among them, compared with traditional static memory, SDRAM memory has a higher integrated Density, higher clock frequency, and lower manufacturing costs have gradually become indispensable functional components for servers, desktops, and handheld embedded systems. Therefore, almost all embedded SoC control chips now integrate SDRAM control structure in order to maximize the performance advantages of SDRAM for specific applications. [0003] Affected by this trend, aerospace and space applications have a...

AI Technical Summary

Problems solved by technology

Obviously, this invention further integrates the spatial continuity between the read operation and the write operation, but it does not explain how to solve the data consistency between the front and back related addresses, so it is not suitable for the processor model of sequential consistency Be applicable

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