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Chip and manufacturing method thereof

A manufacturing method and chip technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems that limit the popularization and application of 3D chips, and avoid granular defects and chip yield reduction and stability Improved effect

Active Publication Date: 2016-11-23
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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  • Claims
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Problems solved by technology

At present, there is no effective method to solve this technical problem in the prior art, making this technical problem one of the important factors limiting the popularization and application of 3D chips

Method used

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  • Chip and manufacturing method thereof
  • Chip and manufacturing method thereof
  • Chip and manufacturing method thereof

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Embodiment Construction

[0033] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0034]It can be seen from the background art that in the manufacturing process of the existing chip, there is a problem that the edge washing process will cause the stability of the chip to decrease. The inventor of the present application has conducted a lot of experimental research on the above problems. By chance, the inventor found that after the edge cleaning process removes the conductive layer in the edge penetrating silicon via, the inner wall of the edge penetrating silicon via is directly exposed. , at this time, the barrier layer on the inner wall of the edge TSV is also directly exposed. The exposed barrier layer is easily damaged, cracked, or even peeled off due to the stress gene...

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Abstract

The invention discloses a chip and a manufacturing method thereof. The chip comprises a substrate, a middle function area and an edge function area, wherein the middle function area is arranged on the substrate and is provided with a middle through silicon via; a barrier layer is formed on the inner wall of the middle through silicon via; the edge function area is arranged on the substrate and is provided with an edge through silicon via; and a barrier layer is formed on the inner wall of the edge through silicon via. The chip also comprises a dielectric layer arranged in the edge through silicon via. The dielectric layer can prevent the inner wall of the edge through silicon via from being exposed directly, thereby preventing the barrier layer on the inner wall of the edge through silicon via from cracking or even shedding due to external stress and the like, preventing granular defects and chip qualified rate reduction due to shedding of the barrier layer and enabling the stability of the chip to be improved.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a chip and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor integrated circuits, the fabrication and packaging of chips have entered into a three-dimensional (3D) space. At present, the production of 3D chips mainly uses through-silicon via technology (TSV) to integrate other devices or chips into a main chip. Generally speaking, TSV is to use an etching process to form a TSV on a main chip, and fill the TSV with a conductive material to integrate other devices or chips into a main chip. [0003] figure 1 It is a structural schematic diagram of an existing 3D chip. Such as figure 1 As shown, the chip includes a plurality of functional regions 200' disposed on a substrate 100', a dielectric layer 214' is disposed in each functional region 200', and various devices disposed in the dielec...

Claims

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Application Information

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IPC IPC(8): H01L23/48H01L21/768
Inventor 方三军陈思安朱瑜杰徐萍
Owner SEMICON MFG INT (SHANGHAI) CORP
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