Digital pulse width modulator based on DCM (Digital Clock Manager) modulation

Abstract

The invention discloses a digital pulse width modulator based on DCM (Digital Clock Manager) modulation. A clock generation module outputs a basic clock signal to a DCM modulation module after performing frequency multiplication on an input clock signal; a synchronous counting module realizes rough modulation of a pulse width by accurately counting zero time delay clock signals, and outputs an initial control signal and a rough modulation control signal to an asynchronous signal generation module and the DCM modulation module respectively at the start and end of the counting; the DCM modulation module outputs a zero time delay clock signal of the basic clock signal to the synchronous counting module, realizes accurate time delay on the basic clock signal at the same time, performs accurate time delay on the rough modulation control signal under the control of a time delay clock signal, and outputs a termination control signal to the asynchronous signal generation module; and the initial control signal and the termination control signal are input into the asynchronous signal generation module, and a final DPWM (Digital Pulse Width Modulation) signal is output. Through adoption of the digital pulse width modulator, accurate phase time delay for the basic clock signal is realized based on the DCM modulation; the modulation accuracy is increased under the condition of constant basic clock signal; and relatively high accuracy, universality and applicability are achieved.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a digital pulse width modulation circuit. Background technique [0002] In the system structure using digital pulse width modulation (Digital Pulse Width Modulation, DPWM), the main methods currently used are hybrid DPWM (Hybrid DPWM), and the second is DPWM realized by Dither method. The DPWM implemented by the Dither method is mainly realized by the idea of ​​​​the design. This design can use a low-precision and high-frequency DPWM to achieve a high effective output accuracy, which also reduces the power consumption and area of ​​​​the DPWM. However, the DPWM realized by the Dither method will generate a cycle delay when the mode is switched, which is not good for the high-speed response of the DPWM, and the design of the hybrid DPWM has no unnecessary delay. [0003] The hybrid DPWM combines the traditional counter structure and the delay chain structure, and ...

AI Technical Summary

Problems solved by technology

However, this method has the following disadvantages: the basic clock signal frequency of this method is only 1MHz, and its structure is complex, the design process requirements are high, and the cost is relatively high

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