Voltage buffer circuit and system capable of quickly increasing output current
A technology of voltage buffering and output current, which is applied in the direction of control/regulation system, adjustment of electrical variables, instruments, etc., to achieve the effect of good reliability and small quiescent current
Active Publication Date: 2017-01-04
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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Problems solved by technology
Obviously, in the current portable devices that are pursuing cost and battery life, this method has exposed great defects. Therefore, it is very practical to design a voltage buffer circuit that quickly builds up a large signal
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[0031] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.
[0032] The following is attached Figure 3-5 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.
[0033] see image 3 , a voltage buffer circuit for rapidly boosting the output current, including: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS tra...
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The invention provides a voltage buffer circuit and a system capable of quickly increasing output current. The voltage buffer circuit is characterized in that a source terminal of a first NMOS (N-channel metal oxide semiconductor) transistor is grounded, a gate terminal is connected with a first offset voltage, and a drain terminal is connected with a source terminal of a second NMOS transistor, a source terminal of a third NMOS transistor and a source terminal of a seventh NMOS transistor; a gate terminal of the second NMOS transistor is connected with the voltage input end, and a drain terminal is connected with a source terminal of a fourth NMOS transistor; a drain terminal of the third NMOS transistor is connected with a source terminal of a fifth NMOS transistor, and the drain terminal of the third NMOS transistor and the source terminal of the fifth NMOS transistor are both connected with the voltage output end, and a gate terminal is connected with the voltage output end; a drain terminal of the fourth NMOS transistor is connected with a power source, a gate terminal is connected with a gate terminal of the fifth NMOS transistor, and the gate terminal of the of the fourth NMOS transistor and the gate terminal of the fifth NMOS transistor are both connected with a drain terminal of a sixth PMOS (P-channel metal oxide semiconductor) transistor, and a drain terminal of the seventh NMOS transistor; a drain terminal of the fifth NMOS transistor is connected with the power source; a gate terminal of the sixth PMOS transistor is connected with a second offset voltage, and a source terminal is connected with the power supply; a gate terminal of the seventh NMOS transistor is connected with the voltage output end.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a voltage buffer circuit for rapidly increasing output current and a system for charging a load. Background technique [0002] Voltage buffer circuits are widely used in current integrated circuit chips, and they are mainly used in analog circuits. When it is necessary to charge and discharge the load capacitance to the required voltage, the voltage supply circuit cannot quickly and accurately charge the load capacitance. When discharging, it is often necessary to insert a voltage buffer circuit between the supply circuit of the voltage and the load capacitance, so as to realize the fast and accurate charge and discharge of the load capacitance to the required specified voltage without causing a large impact on the supply circuit of the voltage. interference. [0003] Conventional voltage snubber circuits such as figure 1 and 2 shown. Figure 1 It is a voltage buf...
Claims
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IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 何学红杨海玲张启帆
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT