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LED epitaxial structure with low dislocation density and residual stress

A residual stress, epitaxial structure technology, applied in electrical components, circuits, semiconductor devices, etc., can solve the problems of high dislocation density and residual stress, affecting the optoelectronic properties of GaN-based LED devices, large lattice mismatch and thermal mismatch, etc. , to achieve the effect of improving crystal quality, improving anti-static ability ESD, and reducing boundary density

Active Publication Date: 2017-01-04
NANTONG TONGFANG SEMICON +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, there is a large lattice mismatch and thermal mismatch between the GaN material with this traditional structure and the substrate, and the GaN film obtained by heteroepitaxy has a high dislocation density and residual stress, which greatly affects the Optoelectronic properties of GaN-based LED devices

Method used

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  • LED epitaxial structure with low dislocation density and residual stress
  • LED epitaxial structure with low dislocation density and residual stress
  • LED epitaxial structure with low dislocation density and residual stress

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Embodiment 1

[0018] In the present invention, the growth temperature of the u-type GaN layer 3 is 900° C., and the growth pressure is 200 mbar. 2 、H 2 or N 2 and H 2 grow in a mixed environment. Both the u-GaN three-dimensional growth layer 3-1 and the u-GaN two-dimensional bulk growth layer 3-2 have a growth thickness of 0.8 um. The alternating growth period of temperature-variable-pressure doped GaN layer 3-3A and temperature-variable-voltage undoped GaN layer 3-3B in u-GaN two-dimensional doped superlattice growth layer 3-3 is 3 periods. The doping element of the growth variable temperature variable pressure doped GaN layer 3-3A is Si, the growth pressure is 200 mbar, and the growth temperature is 950 °C; the growth pressure of the variable temperature variable pressure undoped GaN layer 3-3B is 600 mbar, and the growth The temperature is 900°C. The growth thickness of the variable temperature and voltage variable doped GaN layer 3-3A and the variable temperature and variable press...

Embodiment 2

[0020] In the present invention, the growth temperature of the u-type GaN layer 3 is 1050°C, the growth pressure is 600 mbar, and the 2 、H 2 or N 2 and H 2 grow in a mixed environment. The growth thickness of the u-GaN three-dimensional growth layer 3-1 is 0.8 um, and the growth thickness of the u-GaN two-dimensional bulk growth layer 3-2 is 1.2 um. The alternating growth period of temperature-variable-pressure doped GaN layer 3-3A and temperature-variable-voltage undoped GaN layer 3-3B in u-GaN two-dimensional doped superlattice growth layer 3-3 is 4 periods. The doping element of the growth temperature variable pressure doped GaN layer 3-3A is Si, the growth pressure is 300 mbar, and the growth temperature is 1080 ℃; the doping element of the growth temperature variable pressure doped GaN layer 3-3A is Si, and the growth pressure is is 600 mbar, and the growth temperature is 1000 °C. The growth thickness of the variable temperature and voltage variable doped GaN layer 3...

Embodiment 3

[0022] In the present invention, the growth temperature of the u-type GaN layer 3 is 1100° C., and the growth pressure is 800 mbar. 2 、H 2 or N 2 and H 2 grow in a mixed environment. Both the u-GaN three-dimensional growth layer 3-1 and the u-GaN two-dimensional bulk growth layer 3-2 have a growth thickness of 1.5 um. The alternating growth period of the temperature-variable-pressure doped GaN layer 3-3A and the temperature-variable-pressure undoped GaN layer 3-3B in the u-GaN two-dimensional doped superlattice growth layer 3-3 is 8 periods. The doping element for growing variable temperature variable pressure doped GaN layer 3-3A is Si, the growth pressure is 600mbar, and the growth temperature is 1100°C; the growth pressure for growing variable temperature variable pressure undoped GaN layer 3-3B is 800mbar, and the growth temperature is 1050°C. The growth thickness of the variable temperature variable pressure doped GaN layer 3-3A and the variable temperature variable ...

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Abstract

The invention discloses an LED epitaxial structure with a low dislocation density and a residual stress. The LED epitaxial structure relates to the field of semiconductor luminescence, and sequentially comprises a sapphire substrate, an AlN buffer layer, a u-type GaN layer, an N-type GaN layer, an active layer, an electron blocking layer and a P-type GaN layer from bottom to top. The LED epitaxial structure is characterized in that: the u-type GaN layer sequentially comprises a u-GaN three-dimensional growth layer, a u-GaN two-dimensional block growth layer and a u-GaN two-dimensional doped superlattice growth layer from bottom to top; and the u-GaN two-dimensional doped superlattice growth layer comprises variable-temperature variable-voltage doped GaN layers and variable-temperature variable-voltage undoped GaN layers which grow alternatively from bottom to top, and a doping element in the variable-temperature variable-voltage doped GaN layers is Si. Compared with the prior art, the LED epitaxial structure can effectively reduce the dislocation density and the residual stress through structure change, and improve the photoelectric features of the device.

Description

technical field [0001] The invention relates to the field of semiconductor luminescence, in particular to an LED epitaxial structure capable of reducing dislocation density and residual stress. Background technique [0002] LED is a solid-state semiconductor device that directly converts electrical energy into light energy. GaN-based blue LEDs can be combined with phosphors to generate white light. They have great potential in the field of lighting, and have the characteristics of small size, long life, and fast response. [0003] In the prior art, the blue LED epitaxial structure includes a sapphire substrate 1, an AlN buffer layer 2, a u-type GaN layer 3, an n-type GaN layer 4, an active layer 5, an electron blocking layer 6 and a p-type GaN layer 7, such as figure 1 shown. However, there is a large lattice mismatch and thermal mismatch between the GaN material with this traditional structure and the substrate, and the GaN film obtained by heteroepitaxy has a high disloca...

Claims

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Application Information

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IPC IPC(8): H01L33/02H01L33/04H01L33/12
CPCH01L33/02H01L33/025H01L33/04H01L33/12
Inventor 程腾翟小林俞登永赖志豪曾奇尧林政志
Owner NANTONG TONGFANG SEMICON