Speed grading optimization structure and method capable of improving yield of high-performance integrated circuit

A speed classification, integrated circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of inconsistent maximum operating speed of integrated circuits, and achieve the effect of increasing profits, increasing overall profits, and increasing proportions

A speed classification, integrated circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of inconsistent maximum operating speed of integrated circuits, and achieve the effect of increasing profits, increasing overall profits, and increasing proportions

CN106326535AActive Publication Date: 2017-01-11BEIHANG UNIV

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  • Speed grading optimization structure and method capable of improving yield of high-performance integrated circuit
  • Speed grading optimization structure and method capable of improving yield of high-performance integrated circuit
  • Speed grading optimization structure and method capable of improving yield of high-performance integrated circuit

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Effect test

Embodiment 1

[0100] Apply the internal speed classification optimization structure of the integrated circuit chip designed by the present invention to test:

[0101] The internal speed classification optimization structure of the integrated circuit chip proposed by the present invention has been inserted into several test circuits, such as the FGU (Floating Point and Graphic Unit, floating-point calculation and image processing module) module in the OpenSPARCT2 processor, in ITC'99 The largest circuit b19, and s953, s9234, s13207, s38417, and s35932 of the ISCAS'89 test circuits. The above-mentioned circuits inserted into the on-chip regulation structure have been verified by simulation, and verified on Altera's 28nm FPGA.

[0102] Firstly, the hierarchical optimization structure of single path speed is tested. A path is extracted in the b19 circuit, and the delay of this path is 851ps. The extraction method is as follows: first, use the Design Compiler software of Synopsys to synthesize...

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Abstract

The invention relates to a speed grading optimization structure and method capable of improving the yield of high-performance integrated circuits. The structure is embedded in an integrated circuit and is characterized in that an integrated circuit chip comprises N critical paths, i.e., critical path A, critical path B...critical path N, which jointly form a critical path set [A, B...N], the time delay of the N paths decides the speed grading of the integrated circuit. The adopted method comprises the following steps of: 1. selecting critical paths; 2. inserting an integrated circuit speed grading optimization structure; 3. testing an integrated circuit chip at a frequency boundary Fi; 4) obtaining an original speed grading result; 5. performing speed grading optimization; 6. testing again at the frequency boundary Fi; 7. re-dividing the speed grade of the integrated circuit chip; 8. deciding the speed grade and calculating a speed grading optimization rate; 9. marking the speed grade and working frequency of the integrated chip.

Description

technical field [0001] The present invention relates to an integrated circuit chip speed classification optimization structure and optimization method, more precisely, it is a speed classification optimization structure suitable for improving the output of high-performance integrated circuit chips in the process of integrated circuit chip speed classification and its implementation optimized method. Background technique [0002] An integrated circuit (integrated circuit) is a tiny electronic device or component. It is a semiconductor manufacturing process such as oxidation, photolithography, diffusion, epitaxy, aluminum evaporation, etc., which integrates semiconductors, resistors, capacitors and other components required to form a circuit with certain functions and the connecting wires between them into a small piece of silicon. On-chip, and then welded electronic devices packaged in a tube; all the components have been structurally integrated, making electronic components...

Claims

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Application Information

Patent Timeline
11 Jan 2017
Publication
CN106326535A
IPC
G06F17/50
CPC
G06F30/398
Inventors
王晓晓; 张东嵘