Negative voltage bit line write assistance-based SRAM circuit and method

Abstract

The invention relates to the technical field of electronics, in particular to a static random access memory (SRAM). A negative voltage bit line write assistance-based SRAM circuit comprises N SRAM storage units, a first transistor, a second transistor and a comparison unit, wherein each SRAM storage unit is connected with a first bit line and a second bit line; the first transistor connects the first bit line with a ground voltage or disconnects the first bit line from the ground voltage under the action of a first write enable signal; the second transistor connects the second bit line with the ground voltage or disconnects the second bit line from the ground voltage under the action of a second write enable signal; the comparison unit compares voltage differences of the first bit line and the second bit line under the action of an enable signal, and outputs a first signal and a second signal; a first coupling capacitor is connected between the first signal and the first bit line; a second coupling capacitor is connected between the second signal and the second bit line; and the first signal generates a negative voltage on the first bit line in a coupling manner, or the second signal generates the negative voltage on the second bit line in the coupling manner. According to the SRAM circuit, a control circuit does not need to be singly designed for a bit line negative voltage circuit; in addition, the circuit is simple and the circuit area is saved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a static random access memory. Background technique [0002] figure 1 Shown is the most common SRAM storage unit composed of six transistors. When the voltage of node N1 is high and the voltage of node N0 is low, the value stored in the storage unit is called logic 1, otherwise it is logic 0. When it is necessary to rewrite the data stored in the SRAM storage unit, such as rewriting the stored value 1 to 0, the corresponding operation steps are: first charge the word line WL (Word Line) to a high voltage (generally equal to the power supply voltage VDD), and then The voltage of the bit line BL (Bit Line) is pulled down from the power supply voltage VDD to the ground voltage VSS, and the voltage of the reverse BLB of the bit line is maintained at the power supply voltage VDD; since the driving ability of the PMOS transistor ML1 in the SRAM memory cell is weaker than that of t...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a negative voltage bit line write auxiliary SRAM circuit and method, which overcomes the defects of complex control circuit and large area occupied by the circuit in the chip of the prior art.

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