Transistor forming method

Abstract

The invention discloses a transistor forming method. The method comprises steps: a substrate with a first active region and a second active region is provided, the surface of the substrate is provided with a dielectric layer, the dielectric layer is internally provided with a first opening for enabling partial surfaces of the first active region and the second active region to be exposed, and a gate dielectric layer is arranged on the bottom surface of the first opening; first work function films are formed on the surface of the dielectric layer, and the side wall and the bottom surface of the first opening; work function adjustment processing is carried out on the first work function film in the first active region to enable the first work function film in the first active region to be converted to a second work function film; afterwards, the first work function film and a second work function film on the surface of the dielectric layer are removed, and a second work function layer located in the first active region and a first work function layer located in the second active region are formed; and after the work function adjustment processing, a gate layer filling the first opening is formed in the first opening. The transistor forming process is simplified, and the formed transistor has improved performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] The storage unit of the SRAM includes a 4T (transistor) structure and a 6T (transistor) structure. For a 6T SRAM size unit, it includes: a first PMOS transistor P1 , a second PMOS transistor P2 , a first NMOS transistor N1 , a second NMOS transistor N2 , a third NMOS transistor N3 and a fourth NMOS transistor N4 . Wherein, the P1 and P2 are pull-up transistors; the N1 and N2 are pull-down transistors; and the N3 and N4 are transfer transistors. [0004] In the prior art, in order to su...

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Problems solved by technology

[0006] However, due to the difference in work function layer materials required for PMOS transistors and NMOS transistors, the performance of the formed SRAM is unstable.

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