How the transistor is formed

Abstract

A method for forming a transistor, comprising: providing a substrate having a first active region and a second active region, a dielectric layer is provided on the surface of the substrate, and a portion of the first active region and the second active region are exposed in the dielectric layer. The first opening on the surface of the region, the bottom surface of the first opening has a gate dielectric layer; the first work function film is formed on the surface of the dielectric layer, the sidewall and the bottom surface of the first opening; the first work function film of the first active region The work function film is subjected to work function adjustment treatment, so that the first work function film in the first active region is transformed into a second work function film; after that, the first work function film and the second work function film on the surface of the dielectric layer are removed to form a A second work function layer in the active area, and a first work function layer located in the second active area; after the work function adjustment process, a gate layer filling the first opening is formed in the first opening. The process of forming the transistor is simplified, and the performance of the formed transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] The storage unit of the SRAM includes a 4T (transistor) structure and a 6T (transistor) structure. For a 6T SRAM size unit, it includes: a first PMOS transistor P1 , a second PMOS transistor P2 , a first NMOS transistor N1 , a second NMOS transistor N2 , a third NMOS transistor N3 and a fourth NMOS transistor N4 . Wherein, the P1 and P2 are pull-up transistors; the N1 and N2 are pull-down transistors; and the N3 and N4 are transfer transistors. [0004] In the prior art, in order to su...

AI Technical Summary

Problems solved by technology

[0006] However, due to the difference in work function layer materials required for PMOS transistors and NMOS transistors, the performance of the formed SRAM is unstable.

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