Method of forming semiconductor structure

Abstract

The invention provides a method of forming a semiconductor structure. The method comprises steps of providing a substrate, wherein the surface of the substrate has a separating layer, and a first fin part and a second fin part which are adjacent to each other, the surface of the separating layer is lower than the top surfaces of the first fin part and the second fin part, the first fin part comprises a first side wall and a second side wall which are opposite to each other, and the minimal distance from the second side wall to the side wall of the second fin part is smaller than the minimal distance from the first side wall to the side wall of the second fin part; forming a first mask layer on the surfaces of the separating layer, the second fin part and the first fin part, wherein the first mask layer exposes the first side wall of the first fin part and covers a part of the separating layer of the first side wall; taking the first mask layer as a mask layer, and doping first obstruction ions in the separating layer; and carrying out an annealing process to enable the first obstruction ions in the separating layer to be diffused toward the first fin part. The performance of a fin-type field effect transistor formed by the semiconductor structure is improved, and the mismatch problem of the fin-type field effect transistor is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] The storage unit of the SRAM includes a 4T (transistor) structure and a 6T (transistor) structure. For a 6T SRAM size unit, it includes: a first PMOS transistor P1 , a second PMOS transistor P2 , a first NMOS transistor N1 , a second NMOS transistor N2 , a third NMOS transistor N3 and a fourth NMOS transistor N4 . Wherein, the P1 and P2 are pull-up transistors; the N1 and N2 are pull-down transistors; and the N3 and N4 are transfer transistors. [0004] With the improvemen...

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Problems solved by technology

[0006] However, as the device density in SRAM increases and the size s

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