Detection method and system for E1 link phase jitter

A technology of phase jitter and detection method, which is applied in the field of communication, can solve the problems of expensive phase jitter detection products, and achieve the effect of detection and phase jitter

Inactive Publication Date: 2017-01-25
LIUZHOU DADI TELECOMM EQUIP +1
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Problems solved by technology

[0003] Most of the traditional phase jitter detection methods rely on the mathematical model of jitter, and design related circuits and algorithms with traditional thinking. In order

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  • Detection method and system for E1 link phase jitter
  • Detection method and system for E1 link phase jitter
  • Detection method and system for E1 link phase jitter

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[0048] reference figure 1 , An E1 link phase jitter detection method of the present invention includes the following steps:

[0049] Input the code stream on the E1 link to the E1 interface chip for processing to obtain the NRZ+ signal and NRZ- signal;

[0050] Transmit the NRZ+ signal and NRZ- signal to the FPGA module and restore it to a clock signal with jitter;

[0051] The FPGA module samples the clock signal with jitter to obtain collected data;

[0052] Jitter detection is performed on the collected data through the DSP module, and the detection result is obtained and output.

[0053] reference figure 2 As a further preferred embodiment, the FPGA module samples the clock signal with jitter to obtain collected data. This step includes:

[0054] The FPGA module divides the frequency of the clock signal input by the crystal oscillator to obtain a high-precision clock signal;

[0055] The high-precision clock signal is used as the sampling clock, and the high-precision clock signal is...

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Abstract

The invention discloses a detection method and a detection system for E1 link phase jitter. The method comprises the following steps: processing an input code stream to obtain an NRZ (Non-Return-to-Zero)<+> signal and an NRZ<-> signal; recovering the signals to clock signals with jitter; sampling the clock signals with the jitter to obtain acquired data; and carrying out jitter detection on the acquired data, thus obtaining a detection result and outputting. The system comprises an input code stream processing unit, a jitter signal recovering unit, a data acquisition unit and a jitter detection unit. According to the detection method and system, the offset of a clock is calculated through analyzing a counted value of one clock period so that a phase offset value of the clock is analyzed; the detection result is rapidly calculated through analyzing and processing; high-speed processing properties of an FGPA (Field-Programmable Gate Array) module and a DSP (Digital Signal Processor) module are applied, and high-speed acquisition and high-speed transmission of a jitter signal are realized; and a method based on period counting is combined so that the detection of the phase jitter of the E1 link clock signals is effectively realized. The detection method and system for the E1 link phase jitter can be widely applied to the field of communication.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a detection method and system for E1 link phase jitter. Background technique [0002] In a digital communication system, the short-term, non-accumulative deviation of the effective moment of a digital signal relative to its ideal reference time position is called jitter. Jitter can also be understood as phase modulation or frequency modulation of a digital signal, so it is also called phase jitter. IUT-T G.823 recommends that phase changes above 10 Hz be defined as jitter, and those below 10 Hz as drift. Jitter impairment is one of the important impairments in digital transmission, which will directly affect the reproduction decision of digital signals, leading to an increase in the bit error rate. Therefore, how to quickly and accurately detect jitter becomes very important. [0003] Most of the traditional phase jitter detection methods rely on the mathematical model o...

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Application Information

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IPC IPC(8): H04B17/30
CPCH04B17/30
Inventor 甘智全韦国英黄双
Owner LIUZHOU DADI TELECOMM EQUIP
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