Top gate thin film transistor manufacturing method and top gate thin film transistor

Abstract

The invention provides a top gate thin film transistor manufacturing method and a top gate thin film transistor. The manufacturing method comprises the steps of providing a glass substrate; forming a oxide semiconductor layer on the glass substrate, wherein the oxide semiconductor layer comprises a source region, a drain region and a channel region; forming a gate insulation layer at the position corresponding to the channel region on the oxide semiconductor layer; forming a grid electrode on the gate insulation layer; depositing an interlayer dielectric at the surface of the grid electrode, the surface of the oxide semiconductor layer and the surface of the glass substrate by adopting a method of chemical vapor deposition, and performing conductor processing on the surface of the source region and the surface of the drain region; and forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the source region and the drain region of the oxide semiconductor layer respectively. The manufacturing method has the advantages that conductor processing can be performed when the interlayer dielectric is deposited, and a high migration rate and on-state current can be ensured.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to a method for manufacturing a top-gate thin film transistor and the top-gate thin film transistor. Background technique [0002] In a real device with high resolution and high frame, the TFT of each sub-pixel needs to be fast enough to switch sub-pixels, so TFTs with low parasitic capacitance and high mobility are urgently needed. Oxide semiconductor TFTs have attracted extensive attention due to their high mobility. But so far, the oxide semiconductor TFT mainly adopts the conventional ESL and BCE structures belonging to the bottom gate, and the conventional top gate structure. However, due to the disadvantages of relatively large parasitic capacitance and difficulty in miniaturization, the TFT with the above-mentioned conventional structure cannot be applied to large-size and high-resolution displays. Therefore, the application of self-aligned top-gate TFTs in large-size ...

AI Technical Summary

Problems solved by technology

However, the use of third-party gases for treatment often introduces impurity gases, such as H and F plasmas, which will diffuse to the oxide semiconductor layer in subsequent processes and affect the characteristics of TFTs; on the other hand, if inert gases are used, they often reach Unexpected conductorization effect, the contact resistance between the source / drain 15 (Source / Drain) and the channel region (channel) of the oxide semiconductor layer 12 is still high, which will lead to problems such as low TFT on-state current

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