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3D memory

A memory, three-dimensional technology, applied in semiconductor devices, electrical solid-state devices, electrical components, etc., can solve the problems of limited critical size, storage and storage cell scaling bottlenecks, etc., and achieve the effect of improving integration.

Active Publication Date: 2019-05-31
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the current planar memory (especially the NOR gate) is limited by the critical size of the components in the integrated circuits (integrated circuits), and faces the bottleneck of storage and storage unit scaling.

Method used

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Examples

Experimental program
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Embodiment Construction

[0055] Figure 1A It is a cross-sectional view of a three-dimensional memory according to an embodiment of the present invention. Figure 1B yes Figure 1A Sectional view of the A-A' tangent. Figure 1C yes Figure 1A top view of . Figure 1D yes Figure 1A The schematic diagram of the circuit.

[0056] Please refer to Figure 1A and Figure 1B The three-dimensional memory 110 includes a memory cell stack structure 120 , a plurality of conductive pillars 124 , an interlayer insulating layer 126 , a plug 128 and a plurality of bit lines 130 .

[0057] The stacked memory cell structure 120 is formed by stacking a plurality of memory cell array structures 132 and a plurality of insulating layers 134 alternately. Each memory cell array structure 132 includes a plurality of word lines 136 , a plurality of active layers 138 , a plurality of composite layers 140 and a plurality of source / drain regions 150 .

[0058] The plurality of word lines 136 extend in the Y direction, for e...

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PUM

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Abstract

The invention discloses a three-dimensional memory with a memory unit stack structure. The memory cell stacked structure is composed of multiple memory cell array structures and multiple insulating layers staggered and laminated. Each memory cell array structure has a word line, an active layer, a composite layer and a source / drain region. The word lines, active layers and composite layers extend in the Y direction. The active layer is disposed between adjacent word lines. The composite layer is disposed between adjacent word lines and active layers. Each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in order starting from the active layer. Source / drain regions are arranged at equal intervals in the active layer. The two adjacent source / drain regions, the active layer between the two source / drain regions, and the first dielectric layer, charge storage layer, and second dielectric layer on the active layer The electrical layer and the word line together constitute the memory cell.

Description

technical field [0001] The present invention relates to a semiconductor device, and in particular to a three-dimensional memory. Background technique [0002] As consumer products have higher and higher requirements for storage subsystems, the standards for read / write speed and capacity of products are also getting higher and higher, so high-capacity related products have become the mainstream of the industry. In view of this, it is also necessary to meet this demand in the development of memory. [0003] However, current planar memory (especially NOR memory) is limited by the critical size of components in integrated circuits, and faces a bottleneck in the scaling of memory cells. Therefore, designers are looking for a multi-plane three-dimensional memory (especially a NOR memory) to achieve a larger storage capacity and a lower cost per bit. Contents of the invention [0004] The invention provides a three-dimensional memory, which can improve the integration degree of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11551H10B41/20
Inventor 李致维程政宪古绍泓吕文彬
Owner MACRONIX INT CO LTD