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FPGA-based server acceleration technology

A server and domain technology, applied in the field of FPGA-based server acceleration technology

Inactive Publication Date: 2017-03-29
张洪
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] 3. Cost: The non-recurring engineering (NRE) cost of custom ASIC design far exceeds the cost of FPGA-based hardware solutions
It is very challenging to improve these indicators at the same time, and it is undoubtedly not the best route to rely only on external physical conditions

Method used

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  • FPGA-based server acceleration technology
  • FPGA-based server acceleration technology
  • FPGA-based server acceleration technology

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Embodiment Construction

[0023] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] figure 1 Shown is the FPGA internal structure. It mainly includes 6 parts. They are: embedded RAM, basic programmable logic unit, programmable input and output unit, rich layout and routing resources, complete clock management, embedded dedicated hard core module and embedded underlying functional unit.

[0025] figure 2 Shown is the space-for-time strategy of the FPGA. Taking the multiplication and accumulation operation of the CPU as an example, in order to realize the multiplication and accumulation operation, if the CPU is used to implement it, it is necessary to repeatedly call the multiplication and addition unit of the CPU for 256 clock cycles to have an output. However, if the FPGA is used for processing, the internal resources of the FPGA can be used to implement a multi-engine multiply-accumulator, so that 256 multiply-accumulate operations can ...

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Abstract

Compared with a conventional server, an FPGA has the advantages of parallelism, expandability, flexibility, low cost, long-term maintainability and the like, and certainly becomes a good helper for server acceleration in the future. A development key point of the FPGA in performing acceleration in the field of servers is detailedly surveyed and analyzed. An acceleration scheme involves a hardware structure, board-level design, network design, data center deployment, a software infrastructure, a platform framework and the like. A basic structure and a working principle of the FPGA, advantages and disadvantages of the FPGA, and an acceleration mode of the FPGA for the server are elaborated. Sub-modules such as a software interface, a Shell framework, a Role framework error detection and debugging sub-module and the like are subjected to function description, finally the implementation of a common image processing algorithm is analyzed, and simulation verification is finished by utilizing Vivado HLS software. A simulation result shows that the image processing efficiency can be remarkably improved by adopting an FPGA algorithm in a typical application condition.

Description

technical field [0001] The invention makes full use of the advantages of parallelism, expandability, flexibility, low cost and long-term maintenance of FPGA, and links it with server acceleration. Background technique [0002] With the continuous improvement of the number of logic gates and performance of FPGA, it is widely used in the following occasions: [0003] Connection logic and control logic are areas where FPGAs play a relatively large role in the early days, and they are also the cornerstone of FPGA applications. [0004] Apply relatively mature technology to certain specific fields such as communication, video, information processing, etc. to develop products that meet the needs of the industry and can be accepted by industry customers. FPGA technology is a means of realization in these fields, because it has the characteristics of interface, control, functional IP, and embedded CPU, so it is possible to realize the system product design with simple structure, hi...

Claims

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Application Information

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IPC IPC(8): G06F15/78
Inventor 张洪
Owner 张洪
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