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High-speed and low-power-consumption PAM4 transmitter

A low power consumption, transmitter technology, applied in the direction of electrical components, transmission systems, etc., can solve the problems of consumption, large power consumption, etc., to achieve the effect of reducing power consumption and saving area

Active Publication Date: 2017-04-26
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0005] figure 1 The main problem of the medium transmitter is that when the data rate is very high, before the last stage is combined into a PAM4 signal, it is a cascade of multi-stage 2:1 combiners with NRZ encoding, which still consumes a lot of power. power consumption

Method used

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  • High-speed and low-power-consumption PAM4 transmitter

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Embodiment Construction

[0026] The preferred embodiments will be described in detail below in conjunction with the accompanying drawings. It should be emphasized that the following description is only exemplary and not intended to limit the scope of the invention and its application.

[0027] figure 2 The structure of the PAM4 transmitter proposed by the present invention is shown. Take the data rate of 56Gbit / s (the baud rate of PAM4 encoding is 28GBuad / s) as an example. In the MSB 1 / 4 rate serializer unit, the 4Bit high-order data source sends out 4 channels of NRZ encoded parallel data, and the rate of each channel is 7Gb / s. The 4 channels of data first enter the latch array 1, and after being aligned by the latch array 1, they are sent to the 4:1 combiner 1. The output of the combiner 1 is 1 channel of 28Gb / s NRZ encoded main channel data, which is recorded as MAIN1. At the same time, the 4 channels of data are transmitted to the latch array 2 after passing through the latch array 1, and the...

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Abstract

The invention relates to a high-speed and low-power-consumption PAM4 transmitter used for high-speed serial interfaces, which belongs to the field of analog circuit design. The transmitter is operated based on the PAM4 encoding. In a 8: 2 combiner wherein 8 parallel paths of data are synthesized into 2 paths of data, a 4: 1 combiner is adopted instead of a 8: 4 and 4: 2 two-stage 2: 1 combiner. Therefore, the combiner and corresponding clock link structure is simplified, and the power consumption and the area are greatly saved.

Description

technical field [0001] The invention belongs to the technical field of circuit design and data transmission, and particularly relates to a high-speed and low-power PAM4 transmitter, which is especially suitable for high-speed serial interfaces. Background technique [0002] High-speed serial interface technology has been widely used in wired data transmission. The data rate of single-channel high-speed serial interface continues to rise, and has reached 40Gb / s and above at present. There are two main ways to increase the data rate for single-lane transmission. One is to use NRZ encoding to further increase the speed of clock and data signals. The other is to use four-level pulse amplitude modulation (PAM4) to transmit more data using multi-level coding. [0003] When the transmission data rate is the same, the bandwidth of the NRZ code is 1 / 2 of the data rate, while the bandwidth of the PAM4 code is only 1 / 4 of the data rate. Therefore, compared with the PAM4 transceiver...

Claims

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Application Information

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IPC IPC(8): H04B1/04
CPCH04B1/0483
Inventor 吕方旭王自强张春王志华李福乐
Owner TSINGHUA UNIV
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