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Mask layout and method for forming semiconductor structure

A mask plate and layout technology, which is applied in semiconductor/solid-state device manufacturing, photographic process of patterned surface, and original parts for photomechanical processing, etc. It can solve the problems of complex manufacturing process and semiconductor structure performance that need to be further improved , to achieve reliable electrical connection performance, high position accuracy and shape accuracy, and avoid alignment errors

Active Publication Date: 2017-05-03
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0004] However, the manufacturing process of semiconductor structures with local interconnection structures in the prior art is complicated, and the performance of the formed semiconductor structures needs to be further improved

Method used

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  • Mask layout and method for forming semiconductor structure
  • Mask layout and method for forming semiconductor structure
  • Mask layout and method for forming semiconductor structure

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Embodiment Construction

[0020] It can be seen from the background art that the manufacturing process of the local interconnect structure of the semiconductor structure in the prior art is complicated, and the overall performance of the formed semiconductor structure needs to be further improved.

[0021] refer to figure 1 , figure 1It is a partial perspective view of a semiconductor structure with a local interconnection structure, the semiconductor structure includes: a substrate (not shown); several discrete fins 11 located on the surface of the substrate; a gate structure 12 across the fins 11, and The gate structure 12 covers part of the top surface and the sidewall surface of the fin 11; the source and drain regions (not marked) in the fin 11 located on both sides of the gate structure 12; covers the surface of the gate structure 12 and the dielectric layer 13 on the surface of the source and drain regions; the zeroth metal layer (M0, Metal 0) 14 electrically connected to the source and drain r...

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Abstract

The invention relates to a mask layout and a method for forming a semiconductor structure, wherein the mask layout comprises a first layer of mask layout and a second layer of mask layout; an area between adjacent first graphs is used for defining a source drain area and an isolation area at two sides of a grid structure; graphs formed by projection of the first graphs on the surface of a substrate are first projection graphs; the first projection graphs stretch across multiple active areas in the substrate; an area between adjacent second graphs is used for defining the multiple active areas; the second graphs are used for defining the isolation area positioned between the adjacent active areas; graphs formed by projection of the second graphs on the surface of the substrate are second projection graphs; the second projection graphs stretch across the multiple active areas; the second projection graphs are adjacent to at least one first projection graph; and furthermore, an area among the first projection graphs and the adjacent second projection graphs is used for defining a source drain metal layer, which stretches across surfaces of multiple source drain areas. By means of the mask layout and the method for forming the semiconductor structure disclosed by the invention, the technological flexibility is improved; and the electrical property of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a mask layout and a method for forming a semiconductor structure. Background technique [0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active regions, the interconnection between transistors, or the interconnection between different layers of metal lines, Complete signal transmission and control. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of the semiconductor device and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of various semiconductor devices, a multi-layer interconnection struc...

Claims

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Application Information

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IPC IPC(8): G03F1/00H01L21/768
CPCG03F1/00H01L21/768
Inventor 余云初沈忆华潘见傅丰华
Owner SEMICON MFG INT (SHANGHAI) CORP
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