High-linearity phase interpolator

Abstract

The invention provides a high-linearity phase interpolator. The high-linearity phase interpolator comprises a load circuit, a differential pair set, a main current source bias array and two auxiliary current source bias arrays; the load circuit is connected to an equipotential end; the differential pair set is connected to the load circuit, a first signal input end, a second signal input end, a third signal input end and a fourth signal input end; the main current source bias array is connected to the differential pair set, a quadrant control signal input end, a first phase control signal input end and a first bias voltage input end; and the two auxiliary current source bias arrays are separately connected to the main current source bias array, a second phase control signal input end and a second bias voltage input end. By means of the high-linearity phase interpolator provided by the invention, high-linearity phase output can be obtained.

Description

technical field [0001] The invention relates to the field of phase interpolators, in particular to a high-linearity phase interpolator. Background technique [0002] CDR (Clock Data Recovery Circuit) is a key part of the receiving end of serders (serializer and deserializer). There are usually two structures. One is the CDR based on the phase-locked loop PLL, which also includes the VCO module (Voltage Controlled Oscillator ), the circuit needs to consume more chip area and power consumption; the other type is CDR based on DLL (Delay Locked Loop), but the adjustment range of the voltage control phase of VCDL (Voltage Controlled Delay Line) in DLL is limited, there is The maximum and minimum values, and the TX and RX (sending and receiving ends) of serders usually have a certain frequency mismatch, which causes the phase difference between the sampling clock at the RX end and the clock at the TX end to gradually increase over time, so RX needs a A clock whose phase is adjust...

AI Technical Summary

Problems solved by technology

[0008] The disadvantage of this existing circuit structure is that since the step size of the current between adjacent phases is consistent, thus forming figure 2 In the phase distribution diagram shown in , the corresponding phase angle between adjacent phase points is the phase step between the phase points, and the output phase step near the coordinate axis is obviously smaller than the phase step in the middle of the quadrant, so results in a non-linearity between the output phase

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