Fan-out type wafer-level packaging structure and preparation method thereof

Abstract

The invention provides a fan-out type wafer-level packaging structure and a preparation method thereof. The packaging structure at least comprises a rewiring layer, at least one flip chip, at least two first lug bosses, a plastic package layer and a second lug boss, wherein the flip chip is bonded on the upper surface of the rewiring layer; the first lug bosses are formed on the upper surface of the rewiring layer; the flip chip and the first lug bosses are electrically connected with the rewiring layer; the tops of the first lug bosses are higher than the top of the flip chip; the plastic package layer is formed on the upper surface of the rewiring layer, is used for filling a connecting gap between the flip chip and the rewiring layer and is used for wrapping one part of the flip chip and the first lug bosses; the second lug boss is formed on the lower surface of the rewiring layer. The plastic package layer in the packaging structure provided by the invention is used for supplying seamless bonding and excellent connecting structure between the flip chip and the rewiring layer, so that the interface layering risk is avoided and the reliability of the packaging structure is promoted.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out wafer-level packaging structure and a preparation method thereof. Background technique [0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. Currently, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (Package on Package, POP) and so on. [0003] Fan-out wafer-level packaging is an embedded chip packaging method for wafer-level processing. It is currently one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer-level packaging, fan-out wafe...

AI Technical Summary

Problems solved by technology

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a fan-out wafer level packaging structure and its preparation method, which is used to solve the cumbersome process of the fan-out wafer level packaging method in the prior art, The difficulty and cost are high, and there is a risk of interface delamination in the packaging structure, which affects reliability

Images