Testing circuit and method of weak short circuit fault

Abstract

An embodiment of the invention discloses a testing circuit and method of a weak short circuit fault. The circuit comprises a testing unit (101), a counter (102), a scanning output register (103) and a controller (105), wherein the signal output end of the testing unit (101) is connected with the signal input end of the counter (102), the signal output end of the counter (102) is connected with the signal input end of the scanning output register (103), and the function control end of the controller (105) is respectively connected with the control end of the testing unit (101), the control end of the counter (102) and the control end of the scanning output register (103). The testing circuit of the through-silicon-via weak short circuit fault has the advantages that the circuit is a pure-digital circuit, the internal unit of the circuit can adopt a standard cell library, layout customization is not needed, and constraint on process node transition is avoided.

Description

[0001] 【Technical field】 [0002] The invention relates to the technical field of integrated circuits, in particular to a weak short-circuit fault test circuit and a test method thereof. [0003] 【Background technique】 [0004] The three-dimensional integrated circuit based on TSV (Through Silicon Vias) makes full use of the third dimension of the chip, and vertically interconnects multiple bare chips (Die) through TSV, which not only shortens the length of interconnection lines, but also reduces It is an inevitable trend in the development of integrated circuits to reduce interconnection power consumption and increase chip integration density. As a signal transmission channel between multiple bare chips, TSV's reliability directly affects the yield rate of the entire chip. However, due to the immature TSV preparation process, the stress caused by the thinning of the substrate during the chip manufacturing process, the insufficient filling of the TSV, the growth of the insulat...

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Problems solved by technology

The advantage of this method is that it can detect open circuit and short circuit faults at the same time, but its disadvantage is that the minimum leakage current test threshold is 100uA, that is to say, when the leakage current caused by the short circuit defect is less than 100uA, this method diagnoses that there is no short circuit fault , in the worst case, the leakage current caused by one TSV is 100μA (for no short-circuit fault TSV), then the leakage current caused by 104 TSVs is 1A, assuming that the power supply voltage is 1V, then only the leakage current caused by TSV However, the power consumption of an embedded DSP chip is only about 200mW. Obviously, this test structure is not practical.

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