spi FLASH control chip for command receiving system
A technology for control chips and command reception, applied in general-purpose stored program computers, architectures with a single central processor, climate sustainability, etc., which can solve the problem of different internal handshake data information, risk of use confidentiality, and low resource utilization efficiency. and other issues, to achieve the effect of strong flexibility, ensuring the localization rate, and taking into account the utilization of internal resources of the device
Active Publication Date: 2020-04-28
NO 20 RES INST OF CHINA ELECTRONICS TECH GRP
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Problems solved by technology
[0003] 1. Due to the different manufacturing processes and methods of the receiver in the process of mass production, the internal handshake data information is different, and if the decoding chip uses fixed handshake data information, it cannot communicate with the receiver module, resulting in no response from the system
[0004] 2. Using FPGA, single-chip microcomputer and other high-power components to realize the function of the controller chip, the resource utilization efficiency is low, and the packaging volume is larger than ordinary IC chips
[0005] 3. The use of foreign devices, directly applied to the system, has risks in the use of confidentiality, and faces the risk of embargo
Method used
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[0016] The present invention will be further described below in conjunction with the drawings and embodiments. The present invention includes but is not limited to the following embodiments.
[0017] The SPI FLASH control chip of the present invention integrates a frequency dividing module, a dual-port RAM module, a data verification module, a FLASH interface module, a state machine module and a decoding chip interface module. The frequency division module uses the decode chip clock to generate the frequency division clock, which is provided to the internal modules of the control chip; the state machine module read instruction signal instructs the FLASH interface module to send read instructions, and outputs three SPI signals (chip select, clock, data input) to the outside SPI FLASH is read; the read command is sent, the write enable signal of the state machine module instructs the dual-port RAM module to open the receiving enable, ready for word data reception; the data reception...
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The invention provides an SPI FLASH control chip for a command receiving system. A state machine module instructs a FLASH interface module to perform read operation on external SPI FLASH; the FLASH interface module receives word data and transmits to a two-port RAM module via a word receiving module; the state machine module verifies that a signal is correct or wrong via a data verification module; if the signal is wrong, the FLASH interface module performs data read operation on the external SPI FLASH again; if the signal is correct, the state machine module instructs a decoding chip interface module to perform data read operation on the two-port RAM module. The control chip can meet application requirements of a receiver instruction system, is higher in flexibility, stable in transmission, small in area and simple to apply, has few signal transmission lines and gives consideration to requirements of internal resource use, power consumption and mass production of a device.
Description
Technical field [0001] The invention belongs to the technical field of electronic components, and particularly relates to a digital chip, in particular to a command receiving system SPI FLASH control chip, through which the demand for flexible configuration of internal handshake data of the command receiving system can be realized. Background technique [0002] The existing command receiving system is composed of a power management module, a decoding chip and a receiver. The working principle of the three is as follows figure 1 Shown. According to this system implementation, the decoding chip receives serial port data and outputs handshake data information through the three SPI data lines. The receiver determines whether to reply the decoding chip response operation by comparing whether the handshake data information is consistent with the internal settings. The system application has the following shortcomings: [0003] 1. Due to the different manufacturing processes and methods ...
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IPC IPC(8): G06F15/78
CPCG06F15/7846Y02D10/00
Inventor 陈尔钐操炜鼎陈永良张帆胡霄
Owner NO 20 RES INST OF CHINA ELECTRONICS TECH GRP