A method of manufacturing a storage unit

Abstract

The invention provides a manufacturing method of a storage unit, belonging to the technical field of semiconductor manufacturing, comprising: providing a semiconductor substrate defined with a gate pre-preparation region and a source-drain pre-preparation region, and sequentially forming a floating gate tunnel on the surface of the semiconductor substrate Through the oxide layer, a floating gate polysilicon layer and a floating gate silicon dioxide layer; a first groove is formed on the floating gate silicon dioxide layer above the gate pre-preparation area; the floating gate silicon dioxide layer is removed, and the gate Form a second groove on the floating gate polysilicon layer above the pole pre-preparation area; deposit an ONO layer on the floating gate polysilicon layer; form a control gate layer on the surface of the ONO layer; remove the control gate layer above the source-drain pre-preparation area, The ONO layer and the floating gate polysilicon layer; annealing treatment is performed after the ion implantation process is performed in the source and drain pre-preparation area to form the source and drain. The beneficial effect of the present invention is to increase the contact area between the floating gate and the control gate, and improve the coupling rate between the floating gate and the control gate, thereby improving the writing and erasing efficiency of the storage unit.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a storage unit. Background technique [0002] The coupling ratio (coupling ratio) of the control gate (Control Gate, CG) and the floating gate (Floating Gate, FG) of the storage unit of the flash memory directly affects the writing and erasing efficiency of the floating gate flash memory, and improving the coupling ratio from CG to FG is important for The operating efficiency of floating-gate flash memory is critical. [0003] With the improvement of manufacturing technology, the size of FG has been reduced to the sub-micron level, through the tunnel oxide barrier, electrons (or holes) are injected into FG, and the charge stored in FG changes the threshold voltage of the device, In turn, the data is stored and the CG controls the potential of the FG with this capacitance. The coupling rate between FG and CG is related to the overlap...

AI Technical Summary

Problems solved by technology

[0005] Based on the current process flow, to increase the coupling ratio from CG to FG, it is necessary to reduce the thickness of ONO, which will reduce the storage time of charge at the same time.

Images