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Three-valued NOR gate and three-valued 1-3 wire address decoder based on cnfet

An address decoder and threshold voltage technology, applied in the field of address decoders, can solve problems such as interconnection crosstalk and gate delay

Active Publication Date: 2018-09-18
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The traditional address decoder is designed with CMOS technology. As the feature size shrinks to the nanometer level, problems such as gate delay and interconnect crosstalk caused by interconnection parasitic effects become more and more serious. The working speed of the address decoder encountered great challenges

Method used

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  • Three-valued NOR gate and three-valued 1-3 wire address decoder based on cnfet
  • Three-valued NOR gate and three-valued 1-3 wire address decoder based on cnfet
  • Three-valued NOR gate and three-valued 1-3 wire address decoder based on cnfet

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0023] Embodiment one: if figure 1 and image 3 As shown, a CNFET-based three-value NOR gate, including the first CNFET tube T1, the second CNFET tube T2, the third CNFET tube T3, the fourth CNFET tube T4 and the fifth CNFET tube T5; the third CNFET tube T3 and the fourth CNFET tube T4 are all P-type CNFET tubes, the first CNFET tube T1, the second CNFET tube T2 and the fifth CNFET tube T5 are all N-type CNFET tubes; the grid of the first CNFET tube T1 and the fourth CNFET tube The source of T4 is connected to the first power supply Vdd, the drain of the first CNFET tube T1 is connected to the second power supply Vdd1, and the second power supply Vdd1 is half of the first power supply Vdd; the gate of the second CNFET tube T2 and the third The gate of the CNFET T3 is connected and its connection end is the first input end of a three-value NOR gate; the grid of the fourth CNFET T4 is connected to the gate of the fifth CNFET T5 and its connection end is a three-value NOR gate. ...

Embodiment 2

[0024] Embodiment two: if figure 1 and image 3 As shown, a CNFET-based three-value NOR gate, including the first CNFET tube T1, the second CNFET tube T2, the third CNFET tube T3, the fourth CNFET tube T4 and the fifth CNFET tube T5; the third CNFET tube T3 and the fourth CNFET tube T4 are all P-type CNFET tubes, the first CNFET tube T1, the second CNFET tube T2 and the fifth CNFET tube T5 are all N-type CNFET tubes; the grid of the first CNFET tube T1 and the fourth CNFET tube The source of T4 is connected to the first power supply Vdd, the drain of the first CNFET tube T1 is connected to the second power supply Vdd1, and the second power supply Vdd1 is half of the first power supply Vdd; the gate of the second CNFET tube T2 and the third The gate of the CNFET T3 is connected and its connection end is the first input end of a three-value NOR gate; the grid of the fourth CNFET T4 is connected to the gate of the fifth CNFET T5 and its connection end is a three-value NOR gate. ...

Embodiment 3

[0026] Embodiment three: as figure 1 and image 3 As shown, a CNFET-based three-value NOR gate, including the first CNFET tube T1, the second CNFET tube T2, the third CNFET tube T3, the fourth CNFET tube T4 and the fifth CNFET tube T5; the third CNFET tube T3 and the fourth CNFET tube T4 are all P-type CNFET tubes, the first CNFET tube T1, the second CNFET tube T2 and the fifth CNFET tube T5 are all N-type CNFET tubes; the grid of the first CNFET tube T1 and the fourth CNFET tube The source of T4 is connected to the first power supply Vdd, the drain of the first CNFET tube T1 is connected to the second power supply Vdd1, and the second power supply Vdd1 is half of the first power supply Vdd; the gate of the second CNFET tube T2 and the third The gate of the CNFET T3 is connected and its connection end is the first input end of a three-value NOR gate; the grid of the fourth CNFET T4 is connected to the gate of the fifth CNFET T5 and its connection end is a three-value NOR gate...

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PUM

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Abstract

The invention discloses a CNFET-based (carbon nanotube field effect transistor-based) three-valued NOR gate and a three-valued 1-3 line address decoder. The CNFET-based three-valued NOR gate comprises a first CNFET, a second CNFET, a third CNFET, a fourth CNFET, and a fifth CNFET, and the CNFET-based three-valued 1-3 line address decoder comprises a first CNFET, a second CNFET, a third CNFET, a fourth CNFET, a fifth CNFET, a sixth CNFET, a seventh CNFET, an eighth CNFET, a ninth CNFET, a tenth CNFET, and an eleventh CNFET. The invention has the advantages of low power consumption and short delay.

Description

technical field [0001] The invention relates to an address decoder, in particular to a CNFET-based three-value NOR gate and three-value 1-3 line address decoder. Background technique [0002] Static Random Access Memory (SRAM) has a fast reading and writing speed, and is often used as an interface circuit between a processor and a memory, and as a cache of the processor. With the development of VLSI (Very Large Scale Integration, VLSI), the processor clock frequency increases, which puts forward higher requirements on the read and write speed of SRAM. Address decoder is an important part of SRAM, and its address decoder delay accounts for a large part of SRAM read and write delay, so the read and write speed and power consumption of SRAM have a great influence on the performance of address decoder. relation. The design of the high-performance address decoder plays a great role in improving the reading and writing speed of SRAM and reducing the power consumption. [0003] ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C8/10G11C11/418
CPCG11C8/10G11C11/418
Inventor 汪鹏君龚道辉张会红康耀鹏
Owner NINGBO UNIV