High holding current ldmos structure for high voltage esd protection

Abstract

The invention provides a high sustaining current LDMOS structure for high-voltage ESD protection, including a P-type substrate, an NWELL region, an NP contact region, a thin gate oxide layer on the surface of the P-type substrate, a polysilicon gate electrode, and implantation on the surface of the P-type substrate. The NP source contact area, PP substrate, NTOP layer, the distance between the left edge of the NTOP layer and the right edge of the NP contact area is D1, the distance between the right edge of the NTOP layer and the right edge of the NWELL area is D2, and the device can be adjusted by adjusting D1 To maintain the current, adjust the trigger voltage of the device by adjusting D2. The present invention proposes that the LDMOS device can adjust the trigger voltage through the position of the NTOP layer without changing the process; the change of the position of the NTOP layer can adjust the trigger voltage on the one hand, and the other On the one hand, the holding current can be increased to avoid the latch-up effect; the existence of the NTOP layer can change the current distribution and improve the robustness of the device under the ESD pulse current.

Description

technical field [0001] The invention belongs to the field of electronic science and technology, and is mainly used for the protection technology of Electro Static Discharge (ESD for short), and specifically relates to a high sustaining current LDMOS structure for high-voltage ESD protection. Background technique [0002] ESD stands for Electrostatic Discharge, which is a common phenomenon in nature. ESD exists in every corner of people's daily life. But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits. [0003] For high-voltage integrated circuits, due to the existence of similar latch-up effects, the LDMOS structure ( figure 1 shown) usually cannot be directly used in it. However, if the maintenance voltage of LDMOS is increased to above the VDD voltage by some methods, although it can bring latch-up immunity, it will also increase the voltage that the device can withstand in the on state, coupled with the influence of...

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Problems solved by technology

But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits.

[0003] For high-voltage integrated circuits, due to the existence of similar latch-up effects, the LDMOS structure ( figure 1 shown) usually cannot be directly used in the

However, if the maintenance voltage of LDMOS is increased to above the VDD voltage by some methods, although it can bring latch-up immunity, it will also increase the voltage that the device can withstand in the on state, coupled with the influence of the Kerke effect under high current, LDMOS will quickly produce irreversible damage

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