Thin-film transistor, method for manufacturing same, array substrate and display device

Abstract

The invention discloses a thin-film transistor, a method for manufacturing the same, an array substrate and a display device. An active layer is not in direct contact with the source metal layer and the drain metal layer in the thin-film transistor, thereby reducing the ohmic contact resistance between the active layer and the source metal layer and between the active layer and the drain metal layer, improving an ohmic contact effect between the active layer and the source metal layer and between the active layer and the drain metal layer in the vertical amorphous silicon thin-film transistor, and further improving the operating stability of the thin-film transistor. The embodiment of the invention provides a thin-film transistor comprising the source metal layer, a first ohmic contact layer on the top of the source metal layer, a first insulating layer on the top of the first ohmic contact layer, the active layer on the top of the first insulating layer and in contact with the first ohmic contact layer, a second ohmic contact layer on the top of the active layer; and the drain metal layer on the top of the second ohmic contact layer.

Description

technical field [0001] The present application relates to the field of display technology, in particular to a thin film transistor and a manufacturing method thereof, an array substrate, and a display device. Background technique [0002] At present, high-resolution display products have become the mainstream trend in the market. To achieve high-resolution display of liquid crystal display panels, the requirements for pixel aperture ratio are getting higher and higher. Therefore, reducing the size of thin film transistors (Thin Film Transistor, TFT) has become particularly critical. . In the prior art, there is a vertical TFT structure, which can greatly reduce the size of the TFT, such as figure 1 As shown, the vertical TFT structure includes: a glass substrate 12, a buffer layer 16, a pixel layer 17, a source metal layer 1, a first insulating layer 3, an oxide (IGZO) layer 18, a drain metal layer 6, a second The insulating layer 7 and the gate metal layer 8, wherein the ...

AI Technical Summary

Problems solved by technology

Although figure 1 The vertical TFT structure shown can greatly reduce the size of the TFT, but the vertical TFT structure is only applicable to the oxide TFT at present, and the amorphous silicon is used as the active layer in the amorphous silicon TFT, because the active layer and the source The electrode metal layer and the drain metal layer are in direct contact, so the ohmic contact of the amorphous silicon TFT is poor, resulting in poor stability of the amorphous silicon TFT

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