A kind of semiconductor device and its manufacturing method

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises forming a first fin and a second fin on the surface of a semiconductor substrate; forming a first epitaxial layer doped with first-conduction-type doped impurity and a first liner layer sequentially on the surface of the semiconductor substrate, and exposed surfaces of the first fin and the second fin; removing the first liner layer and the first epitaxial layer in a first area; forming a second epitaxial layer doped with second-conduction-type doped impurity and a cover cap layer sequentially on the surface of the semiconductor substrate corresponding to the first area, and the exposed surface of the first fin; forming a sacrificial layer on the surface of the semiconductor substrate; removing the cover cap layer, the second epitaxial layer, the first liner layer and the first epitaxial layer on the sacrificial layer; removing the sacrificial layer, carrying out an annealing process, and removing the first liner layer and the cover cap layer; and forming a shallow trench shallow tunnel isolation structure on the surface of the semiconductor substrate. According to the invention, damage to the fins caused by ion implantation is avoided, and the performance of the semiconductor device is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, in order to improve the performance of the device, it is necessary to continuously reduce the size of the integrated circuit device. Compared with the existing planar transistors, the FinFET device has more superior performance in channel control and reduction of short-channel effects; the planar gate structure is arranged above the channel, and in the FinFET the gate It is arranged around the fins, so static electricity can be controlled from three sides, and the performance in static electricity control is also more prominent. [0003] There are many methods in the prior art for improving the performance of semiconductor devices, such as forming a super steep retrograde well (Super Steep Retrograde Well, SSRW ...

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Problems solved by technology

However, such a large dose of doping leads to serious damage to the narrow fins, and it is difficult to repair the damage to the fins even with the annealing treatment after ion implantation, and the damaged fins significantly reduce the carrier mobility and De-activation of doping impurities

[0005] In addition, the currently commonly used process is that deep well isolation implantation is performed before fin formation, and Anti-Punch Trough (APT) ion implantation is performed after fin formation. Anti-body breakdown ion implantation is beneficial to control the loss of doping impurities, but a large number of implanted ions can also cause damage to the fins. There are a large number of damage points on the fins. It is found that the damage is especially serious on the top of the fins.

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