Low power power-on reset circuit
A technology of electric reset and circuit, which is applied in the field of circuits, can solve the problems of large resistance area and power consumption, etc., and achieve the effect of reducing resistance area, saving circuit cost, and reducing power consumption
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no. 1 example
[0018] figure 2 It is a schematic circuit structure diagram of a low power consumption POR circuit in the first embodiment of the present invention. Such as figure 2 As shown, the low power consumption POR circuit includes:
[0019] Basic POR circuit 101, switch control part 102 and voltage latch circuit 103;
[0020] The basic POR circuit 101 includes a plurality of voltage dividing resistors for outputting a reset signal when the management voltage is lower than the reference voltage; and outputting a high-level working signal when the management voltage is higher than the reference voltage.
[0021] In this embodiment, the management voltage may specifically be a divided voltage of the power supply voltage, and the reference voltage may specifically be a constant voltage that does not vary with load, power supply, temperature drift, and time variation, wherein the reference voltage may be It is generated by a reference voltage generation circuit or a reference voltage ...
no. 2 example
[0030] This embodiment is optimized on the basis of the above-mentioned embodiments. image 3 A schematic circuit diagram of a low-power POR circuit of the second embodiment is shown in .
[0031] Such as image 3 As shown, the basic POR circuit 101 in the low-power POR circuit specifically includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first N-channel MOS transistor MN1, a second N-channel MOS transistor MN2, a first N-type MOS capacitor MC1, a first inverter I1, a second inverter I2, a third inverter I3, a NAND gate circuit N1 and a comparator circuit C1; wherein,
[0032] The first end of R1 is connected to the power supply voltage VDD through the switch control part, and the second end of R1 is connected to the first end of R2 and the gate of MN1;
[0033] The second end of R2 is connected to the common ground terminal VSS, the source of MN1, the source of MN2, and the source and drain of MC1;
[0034] The first termina...
no. 3 example
[0043] This embodiment is optimized on the basis of the above-mentioned embodiments. Figure 4An actual circuit diagram of a low power consumption POR circuit of the third embodiment is shown in .
[0044] Such as Figure 4 As shown, on the basis of the low power consumption POR circuit provided in the second embodiment, the switch control component is specifically optimized as: P-channel MOS transistor MP1. Wherein, the gate of MP1 is connected to the output terminal of I3, the source of MP1 is connected to VDD, and the drain of MP1 is connected to the first terminal of R1.
[0045] Through the above design, it can be realized that when the circuit system is working normally, the high-level signal output by I3 is loaded to the gate of MP1 so that MP1 is cut off, and the connection between VDD and R1 and R2 is disconnected; at the same time, when the above connection is disconnected Finally, the low-level (or 0-level) voltage on the gate of MN1 makes MN1 cut off, thereby dis...
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