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Low-voltage differential signaling receiving interface and low-voltage differential signaling receiving method

A low-voltage differential and signal receiving technology, applied in electrical digital data processing, instruments, etc., can solve the problems of indeterminate sampling delay time and inability to receive data correctly

Active Publication Date: 2017-07-18
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The main technical problem to be solved by the present invention is to provide a low-voltage differential signal receiving interface and a low-voltage differential signal receiving method to solve the problem that the existing low-voltage differential signal interface cannot determine the sampling rate when the data sampling window exceeds the adjustment range of the delay unit. Delay time, and thus the problem that data cannot be received correctly

Method used

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  • Low-voltage differential signaling receiving interface and low-voltage differential signaling receiving method
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  • Low-voltage differential signaling receiving interface and low-voltage differential signaling receiving method

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Embodiment 1

[0024] This embodiment provides a low-voltage differential signal receiving interface, the low-voltage differential signal receiving interface can be realized by using FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) resources, and the low-voltage differential signal receiving interface can Low-voltage differential signal reception for multiple rates. Of course, the low-voltage differential signal receiving interface in this embodiment is not limited to be realized by FPGA, and may also be realized by other methods. For the low voltage differential signal receiving interface in this embodiment, see figure 1 shown, which includes:

[0025] The delayer 11 is used for delaying the serial sample data (pattern) sent by the sender according to the preset delay step step.

[0026] Delay device 11 in the present embodiment can be realized by the input / output delay unit (IO DELAY) of FPGA, also can realize by other time-delay function circuits certainly; (That is,...

Embodiment 2

[0046] In order to better understand the present invention, this embodiment provides a more specific low-voltage differential signal receiving interface, please refer to image 3 As shown, it includes a delayer 11 , a sampler 12 , a trainer 13 , an alignment adjuster 14 and a clock reset generator 15 . See Figure 4 As shown, the reset generator 15 in this embodiment may include a clock controller 151 , a clock switch enable controller 152 , a clock switch 153 , and a clock division controller 154 . It should be understood that one sampler 12 in this embodiment corresponds to one delayer 11, and there may be multiple sets of delayers 11 and samplers 12 in one low-voltage differential signal receiving interface.

[0047] The delay device 11 in this embodiment is realized by a dedicated input / output delay unit inside the FPGA, and is used to delay the serial sample data sent by the sender according to the preset delay step step. In this embodiment The delay adjustment range of...

Embodiment 3

[0063] This embodiment provides a low voltage differential signal receiving method, please refer to Figure 7 shown, including:

[0064] S701: Perform delay processing on the serial sample data sent by the sender according to a preset delay step.

[0065] The S601 step in the present embodiment can be realized by the input / output delay unit (IO DELAY) of FPGA, certainly also can realize by other delay function circuits; The number of delay steps N) can be flexibly set, for example, it can be set to 128 steps or 256 steps according to actual needs. When the serial sample data sent by the sender is delayed according to the preset delay step, it is gradually adjusted until the corresponding data boundary is found or until the maximum number of delay steps N is reached, and each delay step in this embodiment The specific value of the long step can also be flexibly set according to specific needs, for example, it can be set to 25ps, or 50ps, and so on.

[0066] S702: Sampling th...

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Abstract

The invention discloses a low-voltage differential signaling receiving interface and a low-voltage differential signaling receiving method. The method comprises the following steps of carrying out delay processing on serial sample data sent by a sender according to a preset delay step, carrying out sampling on the serial sample data subjected to delay processing within the delay step and converting the serial sample data into parallel sample data; analyzing the collected parallel sample data, determining a steady state of the corresponding delay step and determining a data boundary; and if the data boundary is not determined when the delay step reaches a preset maximum delay step N and each delay step is in the steady state, directly obtaining delay time corresponding to an N / 2th delay step as sampling delay time to carry out delay setting. When a data sampling window exceeds an adjustable range of a delay unit, if each delay step is in the steady state, the delay time corresponding to the N / 2th delay step is taken as the sampling delay time, so that a best sampling point of the data is determined, and thus the correct reception of transmission data is guaranteed.

Description

technical field [0001] The invention relates to the field of high-speed interfaces, in particular to a low-voltage differential signal receiving interface and a low-voltage differential signal receiving method. Background technique [0002] In the design of digital system interconnection, the traditional parallel bus can no longer meet the needs of high-speed data transmission of the system, and has become the main bottleneck affecting system performance. The emergence of low-voltage differential signaling (Low-Voltage Differential Signaling, LVDS) technology provides the possibility to solve the bottleneck problem of data transmission. [0003] Low-voltage differential signaling technology transmits data with high-speed differential signals with low voltage swings, and can realize point-to-point or point-to-multipoint connections. It has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation. In practical applications, the recepti...

Claims

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Application Information

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IPC IPC(8): G06F13/42
CPCG06F13/4282
Inventor 李成冬龙鲤跃
Owner SHENZHEN PANGO MICROSYST CO LTD
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