Fan-out-type wafer-level packaging structure and preparation method therefor

Abstract

The invention provides a fan-out-type wafer-level packaging structure and a preparation method therefor. The structure comprises a rewiring layer; a first flip chip which is bonded to the upper surface of the rewiring layer; a metal connecting column which is bonded to the upper surface of the rewiring layer; a second flip chip which is bonded to the upper surface of the metal connecting column; a plastic packaging layer which is located on the upper surface of the rewiring layer; a passivation layer which is located on the lower surface of the rewiring layer, wherein the interior of the passivation layer is provided with a plurality of openings; a welding ball convex block which is located in the opening, and is electrically connected with the rewiring layer. In the structure, the lower surface of the rewiring layer is provided with the passivation layer, and the passivation layer can effectively prevent the welding ball convex block in a ball dripping state from moving in a reballing backflow process, thereby guaranteeing the performance of a device in the structure, and improving the yield.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out wafer-level packaging structure and a preparation method thereof. Background technique [0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. Currently, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (Package on Package, POP) and so on. [0003] Fan-out wafer-level packaging is an embedded chip packaging method for wafer-level processing. It is currently one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer-level packaging, fan-out wafe...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a fan-out wafer level packaging structure and a preparation method thereof, which are used to solve the problem of flip-chip in the fan-out wafer level packaging structure in the prior art. The problem of long communication response time between flip-chips caused by the single-layer arrangement of chips, and the problem of over-implantation caused by the formation of solder bumps directly on the surface of the plastic packaging material layer or the surface of the rewiring layer through the lower metallization layer. During the ball reflow process, the solder ball bumps in the ball drop state are easy to move and shift in position, which affects the device performance of the fan-out wafer level packaging structure, and even leads to packaging failure.

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