Method for extracting chip layout features, cmp simulation method and system

Abstract

The invention provides a chip layout feature extraction method and a CMP simulation method and system. When equivalent feature parameter extraction is carried out on panes divided by a chip layout, the proximity effect among the panes of the chip layout in a CMP process is fully considered, a plurality of virtual panes around each pane extend from the pane in the chip layout, and weighted averaging is carried out on graphic feature parameters in the virtual pane area extending from each pane and graphic feature parameters of the pane, so that the extraction precision of equivalent feature parameters of each pane is improved, the correct prediction for the surface appearance of the chip layout is realized, the correctness of CMP process simulation is improved, the efficiency is relatively high, the research and development costs of an integrated circuit are reduced, and the yield of the integrated circuit is ensured.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method for extracting chip layout features, a CMP simulation method and a system. Background technique [0002] For more than half a century, the integrated circuit industry has developed rapidly. Following Moore's Law, the integration density of transistors on a wafer doubles every 18 months, and the corresponding device feature size is simultaneously reduced to 0.7 times. Technology nodes have reached 65nm, 45nm, and even 32nm, 23nm. However, with the continuous shrinking of the feature size of integrated circuits, there are more and more factors affecting chip performance and production yield in the production process. become more prominent. An ideal wafer surface is a prerequisite for smooth lithography. Chemical Mechanical Polishing (CMP, or chemical mechanical planarization) technology is used to planarize the wafer surface in the current VLSI stage. ...

AI Technical Summary

Problems solved by technology

However, in the above-mentioned prior art, when feature extraction is performed on the graphics in each divided pane, there is a deviation when identifying the current pane, such as figure 1 The current pane 10 (20nmx20nm or 10nmx10nm size) is graphically recognized as a dotted pane 11, and there is an offset, which causes a deviation in the graphic features extracted from the current pane 10, which affects the simulation results and reduces the accuracy of the CMP simulation results. accuracy, resulting in lower IC yields

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