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Formation method of semiconductor structure

A semiconductor and dummy gate technology, applied in the field of semiconductor structure formation, can solve problems affecting device performance, transistor junction leakage, etc., and achieve the effects of uniform distribution of doping ions, reducing channel leakage current, and improving performance

Active Publication Date: 2020-03-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the transistors formed by this method still have the problem of junction leakage, which affects the performance of the formed devices.

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0036] In the prior art, when forming the source region or the drain region of a transistor, two implants are performed—shallow implantation called lightly doped drain (Light Doped Drain, LDD) implantation, followed by medium or high dose implantation. source / drain injection. Among them, the lightly doped drain implant uses a large amount of doping material to make the upper surface of the silicon wafer become amorphous. The combination of massive material and surface amorphousness helps maintain shallow junctions, which also help reduce channel leakage.

[0037] However, the leakage current of the transistor formed in the prior art is still relatively large. In the prior art, after lightly doped drain implantation, the distribution of dopant ions in the doped region is uneven and the concentration gradient is large, which affects the performance of the formed shallow junction and the performance of the formed semiconductor structure.

[0038] In order to solve the technical...

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Abstract

A formation method of a semiconductor structure comprises the steps of forming a substrate, wherein the substrate comprises a peripheral region, and the peripheral region is used for forming an input-output device; forming pseudo gate structure on a surface of the substrate, wherein the pseudo gate structure comprises a pseudo gate, a pseudo gate structure arranged on the peripheral region is a peripheral pseudo gate structure; performing a light doping leakage process on the substrate at two sides of the peripheral pseudo gate structure to form a first doping layer; annealing the first doping layer so as to homogenize distribution of doping ions in the first doping layer; forming a source region or a drain region in the substrate at the two sides of the pseudo gate structure; and forming a metal gate structure. After the step of forming the first doping layer, the first doping layer is annealed, so that the distribution of the doping ions in the first doping layer is homogenized, the performance of a first punchthrough prevention layer can be effectively prevented, a shallow junction is favorably maintained, a short channel effect is further prevented, a leakage current of a channel is reduced, and the performance of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] In semiconductor devices, transistors are an important basic device. The basic structure of a transistor includes three main areas: source (Source), drain (Drain) and gate (Gate). Wherein the source and drain are formed by high doping. According to different device types, it can be divided into N-type doping (NMOS) and P-type doping (PMOS). [0003] With the development of integrated circuits to ultra-large-scale integrated circuits, the circuit density inside the integrated circuit is increasing, and the number of components contained in the integrated circuit is also increasing, and the size of the components is also reduced. As the size of the MOS device decreases, the channel of the MOS device shortens accordingly. Due to the shortened channel, the slow-changing channel approximation o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/324
CPCH01L21/324H01L29/66477
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP