A test structure and its layout method

Abstract

The invention relates to semiconductor testing technology, in particular to a test structure and a layout method thereof, in which a plurality of pads are provided and a lower circuit is provided at the bottom of each pad, including a first pad, a second pad, and a first pad. Three pads and a plurality of fourth pads; a plurality of NMOS transistors with the same number and azimuth distribution are arranged in each lower circuit; the sources of all NMOS transistors are connected in parallel to the first pad by using the first set of wiring ; use the second set of wiring to connect the substrates of all NMOS transistors in parallel to the second pad; use the third set of wiring to connect the gates of all NMOS transistors in parallel to the third pad; use the fourth set of wiring to connect The drains of the NMOS transistors at the same position are connected in parallel to a fourth pad, and the NMOS transistors at different positions correspond to different fourth pads, so that multiple test structures can be tested at the same time, and the NMOS transistors in different orientations in the lower circuit can be analyzed The change of the drain current is finally located to the offset direction of the needle insertion position on the probe card.

Description

technical field [0001] The invention relates to semiconductor testing technology, in particular to a testing structure and a layout method thereof. Background technique [0002] With the pursuit of low cost per unit area of ​​integrated circuits and the need for special functional structures, the structural design of CUP (circuit under pad) has gradually emerged. This structure is designed to place active devices such as MOS transistors on the Under the pad to achieve the purpose of saving area. For wafers manufactured using standard manufacturing processes, a test structure (testkey) for testing will be set on the dicing lanes between chips, and the wafer acceptance test is a test of the test structure before the wafer leaves the factory. The stress generated by the probe needle marks will cause the electrical parameters of the CUP to drift (such as threshold voltage, saturation leakage current), which will lead to poor test stability of the test structure. Therefore, the...

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Problems solved by technology

[0003] In the current wafer acceptance test, all the inspections of the pin mark positions are done manually, there are differences in human judgment, there is no system control, and problems cannot be found in time; although there are some test methods in the existing technology, these test methods need to be passed Additional work done

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