Hardware friendly pulse neural network model based on STDP non-supervised learning algorithm

A technology of spiking neural network and unsupervised learning, applied in the field of spiking neural network, can solve the problems of long simulation time, poor scalability, incompatible with parallel processing of biological brain neurons, etc., to achieve simplicity and stability improvement, high reproducibility Sexuality and Expansion Effects

Active Publication Date: 2017-08-25
WUHAN UNIV
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Problems solved by technology

However, most of the current work is concentrated on the computer software platform. On the one hand, due to the summary of previous work, the calculation model of the software platform on the spiking neural network is relatively mature. On the other hand, the development difficulty of the software platform from the learning algorithm to the

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  • Hardware friendly pulse neural network model based on STDP non-supervised learning algorithm
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  • Hardware friendly pulse neural network model based on STDP non-supervised learning algorithm

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[0012] In order to facilitate those of ordinary skill in the art to understand and implement the present invention, the present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the implementation examples described here are only used to illustrate and explain the present invention, and are not intended to limit this invention.

[0013] see figure 1 , a hardware-friendly spiking neural network model based on the STDP unsupervised learning algorithm provided by the present invention is a multi-synaptic delay-forward feedback neural network, and each layer of neurons communicates with other layers through several synapses. Neurons are interconnected, while neurons in each layer are independent of each other. The neuron adopts the impulse response model SRM. The external input signal will cause the change of the cell membrane potential. When the membrane potential exceeds the threshold,...

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Abstract

The invention discloses a hardware friendly pulse neural network model based on an STDP non-supervised learning algorithm. The pulse neural network model is a polysynaptic time-delay forward feedback neural network model, each-layer neural elements are in interconnection with neural elements of other layers through multiple synapses, and internal neural elements of each layer are mutually independent. The model is advantaged in that model design of the pulse neural network is carried out completely based on a digital hardware circuit platform, the STDP non-supervised learning algorithm is innovatively applied to learning training of the pulse neural network model, special functions can be realized, the hardware platform pulse neural network model has relatively high stability, a relatively fast speed is realized on the condition that occupied hardware resources are relatively a few, moreover, a network structure has a parallel connection characteristic, expansibility is substantially improved, and a new concept is provided for realizing a super-scale pulse neural network.

Description

technical field [0001] The invention belongs to the pulse neural network technology, in particular to a hardware-friendly pulse neural network model based on the STDP non-supervised learning algorithm. Background technique [0002] In the biological brain, hundreds of millions of neurons are connected to each other through synapses for information transmission, thereby manipulating individuals to carry out various complex and meticulous biological activities. This kind of nervous system has been studied and imitated by people, and artificial neural networks have also been attention worldwide. In recent years, as the third generation of artificial neural network, spiking neural network has been widely studied due to its amazing biological similarity and powerful computing ability in pattern recognition, image processing, computer vision and other aspects. So far, many scholars have focused on various spiking neural network models and learning mechanisms. These computational ...

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Application Information

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IPC IPC(8): G06N3/04G06N3/063G06N3/08
CPCG06N3/04G06N3/063G06N3/088
Inventor 常胜徐智勇王豪刘锋
Owner WUHAN UNIV
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