Double diffused drain nmos device and manufacturing method

Abstract

The invention discloses a double-diffused drain NMOS device. There is an N-type buried layer on a P-type substrate, and an N-type epitaxy is formed on the N-type buried layer; a P well and a drift region are arranged in the N-type epitaxy, and the It is the channel region of the double diffused drain NMOS device, and the silicon surface above the channel region is the gate oxide layer and the polysilicon gate of the double diffused drain NMOS device; the P well has a moderately doped P-type region and a double diffused drain NMOS device The source region of the drift region has a drain region of a double diffused drain NMOS device; the P well and the drift region also have a P-type doped layer respectively located directly below the source region and the drain region. The P-type doped layer helps to deplete the drift region and increase the breakdown voltage; the P-type doped layer under the source region has little effect on the device, and the threshold voltage is almost unchanged. At the same time, since the concentration of the drift region in the current path is not reduced, it is ensured that the on-resistance of the device will not increase. The process method described in the present invention effectively improves the breakdown voltage without increasing the mask plate, and does not increase the cost.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a double-diffusion drain NMOS device, and also relates to a manufacturing method of the double-diffusion drain NMOS device. Background technique [0002] DDD MOS (Double Diffused Drain MOSFET) high-voltage double-diffused drain devices are widely used in circuit output interfaces, LCD drive circuits, etc., and their operating voltage is about 10-20V. DDD MOS is easily compatible with the traditional CMOS process, the process is simpler than LD MOS, and the manufacturing cost is lower. [0003] Breakdown voltage is particularly important as a key parameter to measure DDD MOS devices. [0004] The structure of the original double diffused drain NMOS device is as follows figure 1 As shown, on the P-type substrate 1 is an N-type buried layer 2 , and on it is an N-type epitaxial layer 3 . The drift region 4 and the P-well 5 are located in the epitaxy 3 . The drift region concentratio...

AI Technical Summary

Problems solved by technology

Usually the drift region cannot be completely depleted resulting in a lower breakdown voltage, but if the breakdown voltage is increased by reducing the concentration of the drift region, the on-resistance will increase

Therefore, usually the two cannot be taken into account, and only a trade-off can be made to obtain a more balanced value.

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