Silicon carbide UMOSFET power device and preparation method thereof
A power device, silicon carbide technology, applied in the field of microelectronics, can solve the problems of gate oxide junction dielectric layer breakdown, reduced device reliability, and gate oxide dielectric maximum electric field peak value, etc., to increase the electron flow width and reduce the electric field. Strength, the effect of contributing to on-resistance
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Embodiment 1
[0045] Such as Figure 1-10 As shown, a silicon carbide UMOSFET power device according to an embodiment of the present invention, its structure includes a drain electrode 8, an N+ substrate layer 1, an N-drift layer 2, an N+ current diffusion layer 3, and a P-type Doped layer 4, source region layer 5, two source electrodes 9; a source region contact layer 10 is arranged between the two source region electrodes 9, and a gate electrode 7 is arranged at the bottom end of the source region contact layer 10, so The outer wall of the gate electrode 7 is wrapped with a gate dielectric 6, and the gate dielectric 6 runs through the N+ current diffusion layer 3, the P-type doped layer 4, and the source region layer 5 in sequence, and the gate dielectric 6 is embedded in the N - top of drift layer 2.
[0046] In this embodiment, the N-drift layer 2 is a drift layer with a gradually changing doping concentration, and the doping concentration gradually increases from the N+ substrate laye...
Embodiment 2
[0065] Such as Figure 1-10 As shown, a silicon carbide UMOSFET power device, its structure includes a drain electrode 8, an N+ substrate layer 1, an N-drift layer 2, an N+ current diffusion layer 3, a P-type doped layer 4, and a source region layer from bottom to top. 5. Two source electrodes 9; a source contact layer 10 is provided between the two source electrodes 9, a gate electrode 7 is provided at the bottom of the source contact layer 10, and the outer wall of the gate electrode 7 is wrapped There is a gate dielectric 6 , which runs through the N+ current diffusion layer 3 , the P-type doped layer 4 , and the source region layer 5 in sequence, and the gate dielectric 6 is embedded on the top of the N-drift layer 2 .
[0066] In this embodiment, the N-drift layer 2 is a drift layer with a gradually changing doping concentration, and the doping concentration gradually increases from the N+ substrate layer 1 to the N+ current diffusion layer 3, and the N-drift layer 2 The...
Embodiment 3
[0086] Such as Figure 1-10 As shown, a silicon carbide UMOSFET power device, its structure includes a drain electrode 8, an N+ substrate layer 1, an N-drift layer 2, an N+ current diffusion layer 3, a P-type doped layer 4, and a source region layer from bottom to top. 5. Two source electrodes 9; a source contact layer 10 is provided between the two source electrodes 9, a gate electrode 7 is provided at the bottom of the source contact layer 10, and the outer wall of the gate electrode 7 is wrapped There is a gate dielectric 6 , which runs through the N+ current diffusion layer 3 , the P-type doped layer 4 , and the source region layer 5 in sequence, and the gate dielectric 6 is embedded on the top of the N-drift layer 2 .
[0087] In this embodiment, the N-drift layer 2 is a drift layer with a gradually changing doping concentration, and the doping concentration gradually increases from the N+ substrate layer 1 to the N+ current diffusion layer 3, and the N-drift layer 2 The...
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Abstract
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