High-speed DAC testing system and method
A test system, high-speed technology, applied in the transmission system, electromagnetic wave transmission system, transmission monitoring, etc., can solve the problems that cannot be evaluated separately, and the high cost of high-speed DAC, and achieve the effect of low cost and simple implementation methods and methods
Active Publication Date: 2017-09-15
XIAMEN UX HIGH SPEED IC
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Problems solved by technology
[0005]
The main purpose of the present invention is to overcome the defect that the cost of testing high-speed DAC in the prior art is too high and cannot be evaluated separately, and propose a high-speed DAC testing system and method, the testing method and steps are simple, and the cost is low
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[0033] The present invention will be further described below through specific embodiments.
[0034] refer to figure 1 , a high-speed DAC test system, including: a simulation module 10, an arbitrary waveform generator 30, a pattern generator 40, a cache circuit 50, a high-speed DAC 60, a high-speed oscilloscope 70, and the like.
[0035] The simulation module 10 includes a DP-QPSK signal source unit 11 , a Labview control unit 12 , a DP-QPSK unit 13 , an optical receiver 14 and a comparison unit 15 . The DP-QPSK signal source unit 11 is used to generate a DP-QPSK data stream, which is input to the arbitrary waveform generator 30 and the pattern generator 40 . The DP-QPSK unit 13 is used to implement DP-QPSK coding and modulation to obtain a DP-QPSK modulated optical signal. The optical receiver 14 is connected with the DP-QPSK unit 13 to decode and restore the DP-QPSK modulated optical signal. The comparison unit 15 is connected with the optical receiver 14 and the DP-QPSK s...
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The invention provides a high-speed DAC testing system and method. The system comprises a simulation module, an arbitrary waveform generator, a code pattern generator, a high-speed cache circuit, a high-speed DAC, and a high-speed oscilloscope, wherein the simulation module is used for generating DP-QPSK data streams, achieving DP-QPSK coded modulation, decoding and recovery, and carrying out comparison for testing; the arbitrary waveform generator is used for receiving the DP-QPSK data streams and outputting clock signals; the code pattern generator is used for receiving the DP-QPSK data streams and outputting low-speed digital signals and control signals; the high-speed cache circuit is used for converting the low-speed digital signals into high-speed digital signals; the high-speed DAC is used for converting the high-speed digital signals into high-speed analog signals according to the clock signals; and the high-speed oscilloscope is used for sending the high-speed analog signals to the simulation module. The system and method provided by the invention has the advantages that the high-speed DAC can be separately tested, an implementation mode and an implementation method are simple, and the implementation cost is low.
Description
technical field [0001] The invention relates to the technical field of optical communication optical fiber transmission systems, in particular to a high-speed DAC testing system and method. Background technique [0002] When 100G enters people's field of vision, how to realize the stable upgrade of the existing 10G system has become the key to people's discussion, and the dual-polarization coherent quadrature phase-shift keying (DP-QPSK) technology not only improves the spectrum utilization, but also reduces the Dependency on Signal Link. [0003] The principle of DP-QPSK code modulation is: the light wave emitted by the CW laser is divided into two light waves with mutually orthogonal polarization states by the polarizer, which are used to modulate two QPSK modulators respectively, and the QPSK modulator is modulated by two Mach-Zehnder There are 4 MZMs in total. Each MZM is driven by a baseband non-return-to-zero electrical signal at a rate of 25Gbps. The two-way quadra...
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IPC IPC(8): H04B10/077H04B10/61H04B17/20H04B17/391H04B17/336H04B1/00
CPCH04B1/0039H04B10/0779H04B10/613H04B17/20H04B17/336H04B17/391
Inventor 肖翔陈哲赵龙李豹程玉华高泉川黄秋伟
Owner XIAMEN UX HIGH SPEED IC