Reliable communication method between hierarchical multi-core processor cores

Abstract

The invention relates to a method for reliable inter-core communication between hierarchical multi-core processors and belongs to the field of communication technology. According to the method, a whole inter-core communication process is divided into five levels for design according to analysis of characteristics of all stages in the inter-core communication process of a multi-core system, and all the levels are responsible for different inter-core communication tasks. Through the method, connection between unified upper user inter-core communication interfaces and flexible bottom hardware is realized; the defects that in an existing inter-core communication mechanism, upper application program interfaces are not unified, and the application range of lower hardware is narrow are overcome; and the demand for performing reliable inter-core communication in a multi-core processor environment is met.

Description

technical field [0001] The present invention relates to the technical field of communication, in particular to a method for reliable communication between hierarchical multi-core processor cores. Background technique [0002] With the continuous development of multi-core architectures, the number of cores integrated on a single chip continues to increase, prompting the shift of the processor design paradigm from computing-centric to communication-centric. Traditional inter-processor core communication schemes, such as bus-based communication, point-to-point communication, and crossbar-based communication, enable communication between a small number of processor cores. However, these schemes all have shortcomings: the communication scheme of the shared bus has a complex hardware structure, the programming is difficult, and it is difficult to achieve global synchronization; the point-to-point communication scheme is difficult to achieve global broadcast of communication signal...

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Problems solved by technology

However, these schemes all have shortcomings: the communication scheme of the shared bus has a complex hardware architecture, the program design is difficult, and it is difficult to achieve global synchronization; the point-to-point communication scheme is difficult to realize the global broadcast of communication signals, which limits its use in multi-core The application under the framework; the communication scheme based on the crossbar has the problem that the area of ​​the hardware chip is not easy to reduce, and the power consumption is relatively large.

[0004] The inter-core communication mechanism proposed in the document "A Design Adapting to the Inter-Core Communication Mechanism of Multi-core Processors" divides tasks only into calculation-type and control-type tasks in a coarse-grained manner, and cannot cover all application requirements.

The three communication channels designed have certain application limitations, cannot be well adapted to various hardware occasions, have poor scalability and portability, and have not proposed a unified upper-layer application abstract interface, which is not conducive to user use

In addition, the communication reliability has not been fully verified, and there may be incomplete communication data

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