Synchronous signal transmission method and device, fpga

Abstract

The invention discloses a synchronous signal transmission method and apparatus, and an FPGA, so that correctness of synchronization signal sampling and usage inside the FPGA can be guaranteed and thus correctness of the whole link data transmission can be ensured. The method comprises: a sampling register in an FPGA receives a synchronization signal transmitted by an input pin of the FPGA and carries out sampling on the synchronization signal, wherein the sampling register is a register at a preset position in the FPGA; and the sampling register sends the sampled synchronization signal to each register using the synchronization signal in the FPGA by each preset signal transmission path meeting a preset time sequence requirement. And the synchronization signal transmitted by the input pin of the FPGA is obtained as follows: a reference clock signal sent to the FPGA based on a need sets the phase of the synchronization signal and then a clock chip arranged outside the FPGA sends the set synchronization signal to the input pin of the FPGA.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a synchronous signal transmission method and device, and a Field Programmable Gate Array (Field Programmable Gate Array, FPGA). Background technique [0002] The JESD204B standard provides a method for establishing an interface between one or more data converters and digital signal processing devices, such as an interface between an Analog to Digital Converter (ADC) and an FPGA, or a digital-to-analog converter (Digital to Analog Converter, DAC) and the interface between the FPGA, compared to the usual parallel data transmission, JESD204B is a higher-speed serial interface. It simplifies the implementation of high-speed converter data interfaces by reducing the number of traces between devices, reducing trace matching requirements, and eliminating setup and hold timing constraints. Since the JESD204B link needs to be established prior to data transmission, new cha...

AI Technical Summary

Problems solved by technology

However, for the above-mentioned second section of routing, since the SYSREF signal enters the FPGA from the input pin of the FPGA, it can theoretically be registered by any register inside the FPGA. Therefore, the transmission delay of the SYSREF signal will increase with each The wiring results vary, so it may happen that the moment when the SYSREF signal arrives at the sampling register inside the FPGA does not meet the setup time of the register, resulting in a sampling error of the SYSREF signal, which in turn causes the local multi-frame clock error of JESD204B, frame and multi-frame Boundary positioning error, the link cannot send or receive data correctly

[0004] To sum up, in the existing JESD204B usage scheme, it is impossible to ensure that the delay of the SYSREF signal from the FPGA input pin to the internal sampling register meets the setup time of the register, so it is impossible to determine the correctness of the sampling of the SYSREF signal inside the FPGA, and thus cannot Ensure the correctness of data transmission

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