Self alignment contact scheme, semiconductor device and method for manufacturing the same

Abstract

An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer. The invention also provides a self alignment contact scheme, a semiconductor device and a method for manufacturing the same.

Description

Technical field [0001] The embodiments of the present invention generally relate to the field of semiconductor technology, and more specifically, to semiconductor structures and methods of forming the same. Background technique [0002] Semiconductor devices are used in various electronic applications, for example, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are usually manufactured by the following steps: successively depositing an insulating or dielectric layer, a conductive layer, and a layer of semiconductor material over a semiconductor substrate; and using photolithography to pattern the multiple material layers to form circuit components and layers thereon element. [0003] The semiconductor industry continues to improve the integration density of individual electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, thereby allowing more c...

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Problems solved by technology

[0004] In particular, as designs shrink, conductive features connected to layers above and below may short out if the conductive features are misaligned

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