Self-aligned contact scheme, semiconductor structure and method of forming same

Abstract

An embodiment is a method comprising: forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls; forming a first hard mask layer over the first gate ; forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a material composition different from that of the first hard mask layer; forming a first dielectric adjacent to and over the first gate layer; etch a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer is exposed in the first opening; fill the first opening with a conductive material; and remove the second hard mask layer masking layer and removing the conductive material and portions of the first dielectric layer overlying the first hard mask layer to form first conductive contacts in the remaining first dielectric layer. The invention also provides a self-aligned contact scheme, a semiconductor structure and a forming method thereof.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of semiconductor technologies, and more particularly, to semiconductor structures and methods of forming the same. Background technique [0002] Semiconductor devices are used in various electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a layer of semiconducting material over a semiconductor substrate; and patterning the multiple layers of material using photolithography to form circuit components and semiconductor devices thereon. element. [0003] The semiconductor industry continues to improve the integration density of individual electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more compon...

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Problems solved by technology

[0004] In particular, as designs shrink, conductive features connected to layers above and below may short out if the conductive features are misaligned

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