Rapidio-based publish/subscribe software bus in FPGA environment

Abstract

The invention discloses a publishing / subscription-based software bus based on RapidIO under an FPGA (Field Programmable Gate Array) environment. The method specifically comprises a RapidIO communication module, a network operation module, a theme management module and an application component, wherein the application component in the same FGPA system is correspondingly connected with the theme management module; the theme management module is correspondingly connected with the RapidIO communication module through the network operation module; different RapidIO communication modules in different FPGA systems are mutually connected through a RapidIO communication link; and the application component carries out bidirectional data transmission with the RapidIO communication module through the theme management module and the network operation module. The software bus shields a complex RapidIO communication interface for the integration of the FPGA system, a publishing / subscription-based data transmission mechanism is adopted, so that the FPGA application components are communicated in a loose coupling way, and the flexibility and the expandability of the FPGA application can be obviously improved.

Description

technical field [0001] The invention relates to electronic engineering applications, in particular to a RapidIO-based publishing / subscribing software bus under the FPGA environment. Background technique [0002] FPGA has been widely used in key fields such as aerospace, communications, and military by virtue of its high computing performance of hardware parallel processing capabilities, rich IO resources, repeatable configuration, short development cycle, low cost, and long-term maintenance. RapidIO, a high-performance, low-pin-count packet-based interconnect architecture, is the only officially licensed embedded interconnect standard. The adoption of the RapidIO-based interconnection architecture is an inevitable trend in the development of interconnection technologies between FPGAs and between FPGAs and other embedded devices. Currently, two major FPGA manufacturers, Altera and Xilinx, have released their configurable RapidIO IP soft cores. To use it in FPGA, you first n...

AI Technical Summary

Problems solved by technology

[0003] During the development process of the FPGA system, it was found that because the design methods and means of the application system under the FPGA architecture are relatively low-level, the interfaces adopted by each application system directly correspond to the application logic, resulting in a large number of interfaces and tight coupling with the hardware. When integrating traditional systems (such as FPGA, PowerPC, etc.), they often face the problem of adapting to heterogeneous interfaces and data formats, which brings huge workload and technical difficulties to system integration.

In addition, FPGA system development requires an in-depth understanding of transmission protocols (such as RapidIO) in order to use the corresponding IP cores, causing application system developers to waste a lot of energy learning proprietary transmission protocols, which greatly increases the development cycle of FPGA application systems

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