Data transmission system and data transmission method based on SoC FPGA

Abstract

The invention relates to the technical field of computer communication and provides a data transmission system and a data transmission method based on the SoC FPGA. The data transmission system based on the SoC FPGA includes an FPGA, an HPS and a DDR, the DDR is hung on the side of the HPS which is internally provided with a processor ARM and a controller DDR, data writing is conducted between the FPGA and the DDR through AMI, data reading is conducted between the HPS and the DDR, and data writing and reading time sequence control is conducted between the FPGA and the HPS through handshake signals h2f-a and h2f-b; the 0 or 1 state of the handshake signal h2f-a corresponds to the empty or full state of the DDR A, and the 0 or 1 state of the handshake signal h2f-B corresponds to the empty or full state of the DDR b so that video data can be uploaded to a host computer. The data transmission is smooth, the speed is high, and a better experience is brought to a user.

Description

technical field [0001] The invention belongs to the technical field of computer communication, and in particular relates to a SoC FPGA-based data transmission system and a data transmission method. Background technique [0002] With the rapid development of information technology, signal processing tasks are becoming more and more heavy, and the requirements for high-speed data transmission are also getting higher and higher, especially when the data transmission volume is large and the data transmission rate is high. The handshake mechanism between devices or communication modules plays a key role in the data transmission process. A variety of relatively mature handshake protocols have appeared before, such as the three most commonly used RS-232 handshake forms: software handshake, hardware handshake and Xmodem. [0003] At present, the FPGA+ARM structure is widely used in digital signal processing, that is, a combination of a separate field-programmable gate array (Field-...

AI Technical Summary

Problems solved by technology

[0004] When the amount of data is large, the data cache needs a large cache space, and the internal storage space of the FPGA is limited, so it is difficult to meet the requirements. If the data is cached through an external memory, the FPGA must perform both write and read operations on the memory. , but also to achieve read data transmission, which has an impact on the data transmission rate

At the same time, there are data lines, address lines, and control lines between the FPGA and the ARM, which require many pins, and the data transmission rate is limited by the chip pins.

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