Convolution, pooling and activation circuit based on resistive random access memory (RRAM) three-dimensional intersection array

A technology of resistive memory and cross array, applied in the field of semiconductor technology and neural network, can solve the problems of long processing time, large plane footprint, and high overhead of two-dimensional cross array of resistive memory, so as to reduce the plane footprint. Area, the effect of reducing power consumption

Active Publication Date: 2017-11-21
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the full serial scheme, since the amount of processing required for the input image is generally much larger than the single processing capacity of the convolution kernel, the processing time required is very long
In the all-parallel scheme, the overhead of the two-dimensional interleaved array of the resistive variable memory is extremely large, and the plane occupies a large area, so it is difficult to be practically applied.
[0006] In addition, there is currently no efficient convolutional neural network hardware implementation that includes convolution, pooling, and activation circuits

Method used

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  • Convolution, pooling and activation circuit based on resistive random access memory (RRAM) three-dimensional intersection array
  • Convolution, pooling and activation circuit based on resistive random access memory (RRAM) three-dimensional intersection array
  • Convolution, pooling and activation circuit based on resistive random access memory (RRAM) three-dimensional intersection array

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Embodiment Construction

[0021] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] figure 1 A schematic structural diagram of a three-dimensional cross array of resistive memory used according to an embodiment of the present invention is shown.

[0023] Such as figure 1 As shown, the three-dimensional cross-point array of the RRAM used in the embodiment of the present invention uses a three-dimensional cross-point architecture (Cross-point Architecture).

[0024] figure 2 A schematic structural diagram...

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Abstract

The invention discloses a convolution, pooling and activation circuit based on a resistive random access memory (RRAM) three-dimensional intersection array, and the circuit comprises a convolution level which comprises the RRAM three-dimensional intersection array; a layer pooling level which comprises N layer pooling level input ends, a layer summation circuit and a layer pooling level output end, wherein the N layer pooling level input ends are connected to N layer convolution sum output ends at the same horizontal layer, and the layer summation circuit carries out the summation of the N layer convolution sums, and enables the summation result to serve as a pooling result and to be outputted to the layer pooling level output; a layer activation level which comprises a layer activation level input end, a layer comparison circuit and a layer activation level output end, wherein the layer activation level input end is connected to the layer pooling level output end, and the layer comparison circuit carries out the comparison of the pooling result and a reference level: outputs the pooling result when the pooling result is greater than the reference level, or else outputs a zero level. The circuit can reduce the power consumption, and reduce the plane occupied area of the circuit.

Description

technical field [0001] The present invention relates to the fields of semiconductor technology and neural network, and more specifically, relates to a convolution, pooling and activation circuit based on a resistive variable memory three-dimensional cross array. Background technique [0002] Because resistive variable memory (RRAM) can change the resistance value of related devices (such as switching between low resistance and high resistance) when the applied voltage changes, and has the advantages of fast speed, high storage density, easy integration, low power consumption, etc. advantages, has received extensive attention in recent years. Convolutional neural network is a powerful neural network that is widely used in the field of image processing such as image classification and recognition, and the field of position detection. [0003] Therefore, if a resistive memory array is used to form a neural network circuit, low hardware overhead and low power consumption can be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G11C13/00
Inventor 康晋锋董镇黄鹏刘晓彦刘力锋
Owner PEKING UNIV
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