Test method and system of control storage chip

A memory chip and testing method technology, applied in error detection/correction, detection of faulty computer hardware, function inspection, etc., can solve the problem that memory interface control module access cannot be finely controlled, cannot be accurately predicted, and processing instruction logic is complex, etc.

Pending Publication Date: 2017-12-08
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, due to the complex logic of the CPU's internal processing instructions, the access to the memory interf...

Method used

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  • Test method and system of control storage chip
  • Test method and system of control storage chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0091] figure 1 A schematic flowchart of a method for controlling a memory chip test provided by an embodiment of the present invention, the method can be executed by a memory interface control module controlling a memory chip test system, wherein the system can be implemented by hardware and / or software , including the following steps:

[0092] Step 101, the CPU pre-stores the first address and the first data in the interface emulation accelerator through the system bus.

[0093] In this embodiment, for example, the CPU may be an ARM processor (Acorn RISC Machine). The ARM processor is a 32-bit RISC processor architecture that is widely used in many embedded system designs. It should be noted that the CPU is connected to the bus system through the instruction bus, the system bus and the data bus, and the interface emulation accelerator is connected to the bus system through the system bus to realize the connection between the interface emulation accelerator and the CPU. Th...

Embodiment 2

[0106] figure 2 It is a schematic flowchart of a testing method for controlling a memory chip provided by an embodiment of the present invention. On the basis of the above-mentioned embodiments, this embodiment further refines the interface simulation accelerator. The interface simulation accelerator includes a pre-stored storage module, a register configuration unit, a data bus host interface control module and a data bus read storage module, such as figure 2 As shown, the method specifically includes the following steps:

[0107] Step 201, the CPU pre-stores the first data in the pre-storage storage module, and sets the first address in the register configuration unit.

[0108] The pre-stored storage module is exemplified by Static Random Access Memory (SRAM), which is a kind of memory with static access function, and can save the data stored in it without refreshing circuit. The advantages of SRAM are high performance and low power consumption.

[0109] Step 202, the r...

Embodiment 3

[0117] image 3 It is a schematic flowchart of a testing method for controlling a memory chip provided by an embodiment of the present invention. In this embodiment, on the basis of the above embodiments, the storage interface control module writes the first data into the memory chip corresponding to the first address according to the first address and the first data. After the steps in the storage unit, it also includes a transmission process between the interface emulation accelerator and the storage interface control module through the instruction bus. Such as image 3 As shown, the method includes the following steps:

[0118] Step 301, the CPU pre-stores the first data in the pre-storage storage module, and sets the first address in the register configuration unit.

[0119] Step 302, the register configuration unit controls the data bus host interface control module according to the received command to write the first data, and sends the first address and the first dat...

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Abstract

The invention discloses a test method and system of a control storage chip. The method comprises: pre-storing, by a CPU (central processing unit), a first address and first data in an interface simulation accelerator through a system bus; transmitting, by the interface simulation accelerator, the first address and the first data to a storage interface control module through a data bus; writing, by the storage interface control module, the first data into a storage unit, corresponding to the first address, of a storage chip; reading, by the interface simulation accelerator, data stored under the first address through the data bus to obtain second data; acquiring, by the CPU, the second data from the interface simulation accelerator, judging whether the second data and the first data are identical or not, and giving a pass to the test if yes. The test method and system according to the technical scheme disclosed herein have the advantages that the interface simulation accelerator is innovatively designed by combining the speed of hardware test with flexibility and controllability of software simulation test, and comprehensive rapid verification of a storage interface control module is achieved via the interface simulation accelerator.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of non-volatile memory, and in particular to a method and system for controlling a memory chip for testing. Background technique [0002] The storage interface control module is an interface control and management module used to connect the CPU or other devices with the storage chip. This module is mainly used to coordinate the read and write commands from the command bus and the data bus, so that they can be reasonably implemented on the memory chip. With the increasing memory capacity, it has always been a difficult point in the industry to comprehensively and quickly verify the interface control unit of the memory. [0003] In the prior art, the verification and simulation work of the storage interface control module is roughly divided into two types. One is to test through software simulation tools. The simulation speed is only a few hertz. Facing the exponentially increasing ...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F11/26
CPCG06F11/2205G06F11/261
Inventor 田佳
Owner GIGADEVICE SEMICON (BEIJING) INC
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