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Method For Integrating Germanides In High Performance Integrated Circuits

A technology of integrated circuits and channel regions, applied in circuits, electrical components, semiconductor devices, etc., can solve problems such as GeNMOSFET differential drive current

Inactive Publication Date: 2017-12-08
LAM RES CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, Ge NMOSFETs suffer from poor drive current due to high parasitic resistance

Method used

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  • Method For Integrating Germanides In High Performance Integrated Circuits
  • Method For Integrating Germanides In High Performance Integrated Circuits
  • Method For Integrating Germanides In High Performance Integrated Circuits

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Experimental program
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Embodiment Construction

[0063] As mentioned above, double silicide can be realized on Si. The work function (Fermi level) of the silicide is pinned by the contact material and tailored to reach the band edge. Candidates are: PMOSFET>0.8eV=Ir, Pt, Os, and NMOSFETfigure 1 This applies to Si as shown by T. Nishimura, K. Kita and A. Toriumi in Applied Physics Letter, 91, 123123 (2007). However, in the case of substrates using Ge, all metals contacting Ge fall within a narrow range within the bandgap due to Fermi level pinning.

[0064] now refer to figure 2 , the electron barrier height is not significantly modulated by changing the metal work function, and remains about 0.58 eV for Ge, as described by A. Dimoulas, P. Tsipas and A. Sotiropoulos in Applied Physics Letter 89, 252110 (2006) .

[0065] now refer to image 3 , if N-type Ge can be passivated and P-type Ge is not passivated, a single metal material can generate two work functions (see image 3 circled area in ). A Thatachary et al., Appl...

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Abstract

The present invention relates to a method for integrating germanides in high performance integrated circuits. A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and p-type metal oxide semiconductor field effect transistors (PMOSFETs), wherein channel regions of the NMOSFETs and the PMOSFETs include germanium; b) depositing and patterning a mask layer to mask the channel regions of the PMOSFETs and to not mask the channel regions of the NMOSFETs; c) passivating an exposed surface of the substrate; d) removing the mask layer; and e) depositing a metal contact layer on both the NMOSFETs and the PMOSFETs.

Description

technical field [0001] The present disclosure relates to methods of substrate processing, and more particularly to methods for integrating germanium in high performance integrated circuits. Background technique [0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. To the extent described in this Background section and aspects that would not otherwise be considered a description of prior art at the time of filing, the work of the presently named inventors is neither expressly nor implicitly admitted to be relevant to this Published prior art. [0003] P-channel metal oxide semiconductor field effect transistors (PMOSFETs) and n-channel MOSFETs (NMOSFETs) are used in many high performance integrated circuits. Reducing contact resistance is important to further improve performance. Although nickel silicide (NiSi) provides good contact resistance, NiSi includes Si as an intermediate gap work function mate...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L29/10
CPCH01L21/823807H01L21/823878H01L29/1033H01L21/28512H01L29/66651H01L29/161H01L27/092H01L29/0673H01L29/1054H01L29/42392H01L29/78696H01L21/823821H01L21/823412H01L21/82345H01L21/027H01L21/0245
Inventor 保罗·雷蒙德·贝塞尔索斯藤·利尔
Owner LAM RES CORP