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Mask layer structure, semiconductor device and manufacturing method thereof

A manufacturing method and mask layer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of increasing the process window, improving yield and performance

Active Publication Date: 2020-05-15
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] As the size of semiconductor devices continues to shrink, the critical dimension (CD, Critical Dimension) of lithography is gradually approaching or even exceeding the physical limit of optical lithography, which poses more severe challenges to semiconductor manufacturing technology, especially lithography technology.

Method used

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  • Mask layer structure, semiconductor device and manufacturing method thereof
  • Mask layer structure, semiconductor device and manufacturing method thereof
  • Mask layer structure, semiconductor device and manufacturing method thereof

Examples

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Effect test

Embodiment 1

[0052] As an example, such as Figure 3A and Figure 3B As shown, the mask layer structure based on the self-aligned double pattern of the present invention includes: a substrate (not shown), and a core mask layer pattern 30 formed on the substrate.

[0053] Wherein, the substrate may include a semiconductor substrate, and the semiconductor substrate may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), germanium-on-insulator Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0054] Optionally, the substrate further includes a front-end device formed on the semiconductor substrate, the front-end device can be a transistor, the transistor can be used to form various circuits, and the transistor can be an ordinary transistor, a high-k metal gate transistors, fin transistors, or other suitable transistors.

[0055] The front-end device may also include various o...

Embodiment 2

[0088] Below, refer to Figure 4A to Figure 4D A specific embodiment of the aforementioned method for manufacturing a semiconductor device will be described in detail.

[0089] The manufacturing method of the semiconductor device of the present invention is based on the SADP process, which can be used for manufacturing metal wires. In this embodiment, the manufacturing method of the present invention is mainly introduced in detail by taking the manufacturing process of metal wires as an example.

[0090] First, if Figure 4A As shown, a substrate (not shown) is provided on which a nuclear mask layer pattern 30 is formed.

[0091] Wherein, the substrate may include a semiconductor substrate, and the semiconductor substrate may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), germanium-on-insulator Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0092] Opti...

Embodiment 3

[0132] The present invention also provides a semiconductor device formed by the above-mentioned manufacturing method, the semiconductor device includes a metal wire pattern, the metal wire pattern includes a plurality of metal wires extending along the first direction, and a cut-off area is provided in the central area of ​​the metal wire pattern. There are several metal wires extending along the first direction, and the number of the cut metal wires is an even number.

[0133] Since the semiconductor device of the present invention is manufactured by the aforementioned method, the semiconductor device of the present invention also has the same advantages on the premise that the aforementioned method has excellent technical effects.

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Abstract

The invention provides a mask layer structure, a semiconductor device and a manufacturing method thereof. The mask layer structure comprises a substrate and a core mask layer pattern formed on the substrate. The core mask layer pattern comprises a plurality of first sub-core mask layer patterns, a second sub-core mask layer pattern, third sub-core mask layer patterns and fourth sub-core mask layer patterns, wherein the first sub-core mask layer patterns extend along a first direction and are spaced from each other; one end of the second sub-core mask layer pattern is connected with the sidewall of one first sub-core mask layer pattern, the second sub-core mask layer pattern extends along a second direction, and the other end of the second sub-core mask layer pattern is not connected with any first sub-core mask layer pattern; two sides of the second sub-core mask layer pattern are provided with a plurality of the third sub-core mask layer patterns and fourth sub-core mask layer patterns spaced from one another, each of the third sub-core mask layer patterns and the fourth sub-core mask layer patterns extends along the first direction, and the fourth sub-core mask layer patterns are spaced from the second sub-core mask layer pattern.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a mask layer structure, a semiconductor device and a manufacturing method thereof. Background technique [0002] As the size of semiconductor devices continues to shrink, the critical dimension (CD, Critical Dimension) of lithography is gradually approaching or even exceeding the physical limit of optical lithography, which poses more severe challenges to semiconductor manufacturing technology, especially lithography technology. The double composition technology also came at the right time. The basic idea is to divide the target pattern into two, and obtain the lithography limit that cannot be obtained by single exposure through two exposures. [0003] Self-aligned double patterning (Self-aligned double patterning, SADP) technology belongs to a kind of double patterning technology, the main principle of SADP technology is: first form spacers on both sides of the photoresis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027
CPCH01L21/027
Inventor 宋长庚周朝锋李晓波
Owner SEMICON MFG INT (SHANGHAI) CORP
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