Semiconductor device with stacked layout

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

Description

[0001] Cross References to Related Applications [0002] This application claims foreign priority from European Application No. 16174252.3 filed on June 13, 2016, the content of which is hereby incorporated by reference in its entirety. [0003] background technical field [0004] The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices having stacked arrangements, and also to methods of fabricating such devices. Background technique [0005] The demand for reduced device footprint per memory cell or bit in memory devices and for increased circuit density continues to demand reductions in the gate lengths of transistors of memory devices. Scaling of memory cells also continues to require reduced routing pitch and increased number of lithographic exposures to meet design constraints. However, continued scaling increases the difficulty of manufacturing and / or the difficulty of meeting desired performance and / or energ...

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Problems solved by technology

However, continued scaling increases the difficulty of manufacturing

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