A clock recovery method and device

Abstract

The invention relates to a clock recovery method and a clock recovery device. The method comprises the steps of determining a hopping point before a current analysis point in a tested signal; computing the number of current delay points according to an identifier of the current analysis point, an identifier of the hopping point and a half of sampling points in a period where the current analysis point is located; computing a difference between the number of the current delay points and the stored number of the delay points computed in last time to acquire a current phase increment; adjusting the current analysis point according to the current phase increment, and using the adjusted analysis point as the new current analysis point; comparing the current phase increment with the stored phase increments acquired by computing in the preset previous times, when the phase increments are the same, ending a clock recovery operation; and when the phase increments are different, repeating the step of performing clock recovery according to the new current analysis point. According to the technical scheme of the method, influence of hardware equipment on clock recovery accuracy is eliminated, accuracy of a clock recovery result is improved, the method is completely achieved by software, cost is greatly reduced, and a relatively quick clock recovery speed is achieved.

Description

technical field [0001] The present disclosure relates to the technical field of signal processing, and in particular to a clock recovery method and device. Background technique [0002] The method of recovering the clock component from the transmitted signal is called clock recovery. At present, the clock recovery of high-speed serial signals is often realized by hardware. For example, companies such as Agilent and LeCroy use a clock recovery method based on a hardware phase-locked loop. The method manifests itself as a closed-loop negative feedback phase control system that keeps the output and input signals synchronized in phase and frequency. In the locked state, the phase difference between the output signal generated by the voltage-controlled oscillator and the input signal is a constant. Figure 11 It is the basic principle diagram of the phase-locked loop, such as Figure 11 as shown, [0003] The feedback system of the phase-locked loop consists of the following th...

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Problems solved by technology

[0007] However, the biggest bottleneck of the existing technology is that the hardware phase-locked loop clock recovery will affect the accuracy of the recovered clock due to the jitter components generated by the firmware itself.

The difficulty is that the hardware phase-locked loop clock recovery is composed of three hardware parts: phase detector, loop filter, and voltage-controlled oscillator. Generally, the setting of these parameters is realized through the control of resistors and capacitors.

However, inside the circuit, due to the influence of temperature, device aging and other issues, the parameters will change to a certain extent, which will affect the accuracy of the results.

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